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SX1211 transceiver ultra-low power integrated uhf transceiver advanced communications & sensing rev 7C september 2 nd , 2008 page 1 of 92 www.semtech.com general description the SX1211 is a low cost single-chip transceiver operating in the frequency ranges from 863-870, 902 - 928 mhz and 950-960 mhz. the SX1211 is optimized for very low power consumption (3ma in receiver mode). it incorporates a baseband modem with data rates up to 200 kb/s. data handling features includ e a sixty-four byte fifo, packet handling, automatic cr c generation and data whitening. its highly integrate d architecture allows for minimum external component count whilst maintaining design flexibility. all ma jor rf communication parameters are programmable and most of them may be dynamically set. it complies wi th european (etsi en 300-220 v2.1.1) and north american (fcc part 15.247 and 15.249) regulatory standards. ordering information table 1: ordering information part number delivery minimum order quantity / multiple SX1211i084trt tape & reel 3000 pieces SX1211i084t tray 200 pieces tqfn-32 package C operating range [-40;+85c] t refers to lead free packaging this device is weee and rohs compliant features low rx power consumption: 3ma low tx power consumption: 25 ma @ +10 dbm good reception sensitivity: down to -107 dbm at 25 kb/s in fsk, -113 dbm at 2kb/s in ook programmable rf output power: up to +12.5 dbm in 8 steps packet handling feature with data whitening and automatic crc generation wide rssi (received signal strength indicator) dynamic range, 70db from rx noise floor bit rates up to 200 kb/s, nrz coding on-chip frequency synthesizer fsk and ook modulation incoming sync word recognition built-in bit-synchronizer for incoming data and clock synchronization and recovery 5 x 5 mm tqfn package optimized circuit configuration for low-cost applications applications wireless alarm and security systems wireless sensor networks automated meter reading home and building automation industrial monitoring and control remote wireless control application circuit schematic
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 2 of 92 www.semtech.com table of contents 1. general description............................. ..................................... 5 1.1. simplified block diagram ...................... ................................. 5 1.2. pin diagram................................... ........................................ 6 1.3. pin description ............................... ....................................... 7 2. electrical characteristics ...................... .................................... 8 2.1. esd notice.................................... ........................................ 8 2.2. absolute maximum ratings ...................... ............................. 8 2.3. operating range ............................... .................................... 8 2.4. chip specification............................ ...................................... 8 2.4.1. power consumption ........................... ................................ 8 2.4.2. frequency synthesis ......................... ................................. 9 2.4.3. transmitter ................................. ........................................ 9 2.4.4. receiver .................................... ....................................... 10 2.4.5. digital specification ....................... ................................... 11 3. architecture description........................ .................................. 12 3.1. power supply strategy ......................... ............................... 12 3.2. frequency synthesis description............... .......................... 13 3.2.1. reference oscillator ........................ ................................. 13 3.2.2. clkout output ............................... ................................ 13 3.2.3. pll architecture ............................ ................................... 14 3.2.4. pll tradeoffs ............................... .................................... 14 3.2.5. voltage controlled oscillator............... .............................. 15 3.2.6. pll loop filter ............................. .................................... 16 3.2.7. pll lock detection indicator ................ ............................ 16 3.2.8. frequency calculation ....................... ............................... 16 3.3. transmitter description....................... ................................. 18 3.3.1. architecture description.................... ................................ 18 3.3.2. bit rate setting............................ ..................................... 19 3.3.3. alternative settings........................ ................................... 19 3.3.4. fdev setting in fsk mode .................... ............................ 19 3.3.5. fdev setting in ook mode .................... ........................... 19 3.3.6. interpolation filter........................ ..................................... 20 3.3.7. power amplifier ............................. ................................... 20 3.3.8. common input and output front-end ........... .................... 22 3.4. receiver description.......................... .................................. 23 3.4.1. architecture ................................ ...................................... 23 3.4.2. lna and first mixer ......................... ................................. 24 3.4.3. if gain and second i/q mixer................ ........................... 24 3.4.4. channel filters ............................. .................................... 24 3.4.5. channel filters setting in fsk mode ......... ....................... 25 3.4.6. channel filters setting in ook mode ......... ...................... 26 3.4.7. rssi........................................ ......................................... 26 3.4.8. fdev setting in receive mode ................ .......................... 28 3.4.9. fsk demodulator ............................. ................................ 28 3.4.10. ook demodulator ............................ .............................. 28 3.4.11. bit synchronizer ........................... .................................. 31 3.4.12. alternative settings....................... .................................. 32 3.4.13. data output ................................ .................................... 32 4. operating modes ................................. ................................... 33 4.1. modes of operation ............................ ................................. 33 4.2. digital pin configuration vs. chip mode ....... ........................ 33 5. data processing ................................. .................................... 34 5.1. overview ...................................... ....................................... 34 5.1.1. block diagram ............................... ................................... 34 5.1.2. data operation modes........................ .............................. 34 5.2. control block description..................... ................................ 35 5.2.1. spi interface............................... ...................................... 35 5.2.2. fifo ........................................ ......................................... 38 5.2.3. sync word recognition ....................... ............................. 40 5.2.4. packet handler .............................. ................................... 40 5.2.5. control..................................... ......................................... 40 5.3. continuous mode ............................... ................................. 41 5.3.1. general description ......................... ................................. 41 5.3.2. tx processing ............................... .................................... 41 5.3.3. rx processing............................... .................................... 42 5.3.4. interrupt signals mapping ................... .............................. 42 5.3.5. uc connections .............................. .................................. 43 5.3.6. continuous mode example ..................... .......................... 43 5.4. buffered mode ................................. .................................... 44 5.4.1. general description ......................... ................................. 44 5.4.2. tx processing ............................... .................................... 44 5.4.3. rx processing............................... .................................... 45 5.4.4. interrupt signals mapping ................... .............................. 46 5.4.5. uc connections .............................. .................................. 47 5.4.6. buffered mode example....................... ............................. 47 5.5. packet mode................................... ..................................... 49 5.5.1. general description ......................... ................................. 49 5.5.2. packet format ............................... ................................... 49 5.5.3. tx processing ............................... .................................... 51 5.5.4. rx processing............................... .................................... 51 5.5.5. packet filtering ............................ ..................................... 52 5.5.6. dc-free data mechanisms..................... .......................... 53 5.5.7. interrupt signal mapping .................... ............................... 54 5.5.8. uc connections .............................. .................................. 55 5.5.9. packet mode example ......................... ............................. 56 5.5.10. additional information ..................... ................................ 56 6. configuration and status registers.............. ........................... 58 6.1. general description ........................... .................................. 58 6.2. main configuration register - mcparam......... ..................... 58 6.3. interrupt configuration parameters - irqparam . ................. 60 6.4. receiver configuration parameters - rxparam ... ................ 62 6.5. sync word parameters - syncparam.............. ................... 63 6.6. transmitter parameters - txparam .............. ....................... 64 6.7. oscillator parameters - oscparam .............. ....................... 64 6.8. packet handling parameters C pktparam ......... ................. 65 7. application information ......................... .................................. 66 7.1. crystal resonator specification ............... ............................ 66 7.2. software for frequency calculation ............ ......................... 66 7.2.1. gui ......................................... .......................................... 66 7.2.2. .dll for automatic production bench ......... ......................... 66 7.3. switching times and procedures................ ......................... 66 7.3.1. optimized receive cycle ..................... ............................. 67 7.3.2. optimized transmit cycle .................... ............................. 68 7.3.3. transmitter frequency hop optimized cycle ... ................. 69 7.3.4. receiver frequency hop optimized cycle...... .................. 70 7.3.5. rx tx and tx rx jump cycles ..................................... 71 7.4. reset of the chip ............................. .................................... 72 7.4.1. por......................................... ......................................... 72 7.4.2. manual reset................................ .................................... 72 7.5. reference design .............................. .................................. 73 7.5.1. application schematic....................... ................................ 73 7.5.2. pcb layout .................................. .................................... 73 7.5.3. bill of material ............................ ...................................... 74 7.5.4. saw filter plot ............................. .................................... 75 7.5.5. ordering information for tools .............. ............................ 75 7.6. reference design performance .................. ......................... 76 7.6.1. sensitivity flatness ........................ ................................... 77 7.6.2. sensitivity vs. lo drift.................... ................................... 78 7.6.3. sensitivity vs. receiver bw ................. ............................. 79 7.6.4. sensitivity stability over temperature and v oltage............ 80 7.6.5. sensitivity vs. bit rate .................... .................................. 80 7.6.6. adjacent channel rejection.................. ............................ 81 7.6.7. output power flatness....................... ............................... 82 7.6.8. pout and idd vs. pa setting ................. ............................ 83
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 3 of 92 www.semtech.com 7.6.9. pout stability over temperature and voltage . ................... 84 7.6.10. transmitter spectral purity ................ ............................. 85 7.6.11. ook channel bandwidth...................... .......................... 86 7.6.12. fsk spectrum in europe ..................... ........................... 87 7.6.13. digital modulation schemes................. ........................... 88 7.6.14. current stability over temperature and volt age ............. 89 8. packaging information ........................... ................................. 90 8.1. package outline drawing....................... .............................. 90 8.2. pcb land pattern.............................. .................................. 90 8.3. tape & reel specification..................... ............................... 91 9. revision history................................ ...................................... 92 10. contact information ............................ .................................. 92 index of figures figure 1: SX1211 simplified block diagram .......... ....................... 5 figure 2: SX1211 pin diagram ....................... .............................. 6 figure 3: SX1211 detailed block diagram............ ...................... 12 figure 4: power supply breakdown................... ......................... 13 figure 5: frequency synthesizer description........ ...................... 14 figure 6: lo generator ............................. ................................. 14 figure 7: loop filter .............................. ..................................... 16 figure 8: transmitter architecture ................. ............................. 18 figure 9: i(t), q(t) overview ...................... .................................. 18 figure 10: pa control .............................. ................................... 21 figure 11: optimal load impedance chart ............ ..................... 21 figure 12: recommended pa biasing and output match ing ..... 22 figure 13: front-end description ................... ............................. 22 figure 14: receiver architecture ................... ............................. 23 figure 15: fsk receiver setting .................... ............................ 23 figure 16: ook receiver setting .................... ........................... 23 figure 17: active channel filter description ....... ........................ 24 figure 18: butterworth filter's actual bw .......... ......................... 26 figure 19: polyphase filter's actual bw ............ ......................... 26 figure 20: rssi dynamic range...................... .......................... 27 figure 21: rssi irq timings ........................ ............................. 28 figure 22: ook demodulator description............. ...................... 29 figure 23: floor threshold optimization ............ ......................... 30 figure 24: bitsync description..................... ............................... 31 figure 25: SX1211s data processing conceptual view ............. 34 figure 26: spi interface overview and uc connection s ............. 35 figure 27: write register sequence ................. .......................... 36 figure 28: read register sequence.................. ......................... 37 figure 29: write bytes sequence (ex: 2 bytes) ...... ..................... 37 figure 30: read bytes sequence (ex: 2 bytes)....... .................... 38 figure 31: fifo and shift register (sr) ............ ......................... 38 figure 32: fifo threshold irq source behavior ...... ................. 39 figure 33: sync word recognition ................... .......................... 40 figure 34: continuous mode conceptual view ......... .................. 41 figure 35: tx processing in continuous mode........ .................... 41 figure 36: rx processing in continuous mode ........ ................... 42 figure 37: uc connections in continuous mode....... .................. 43 figure 38: buffered mode conceptual view........... ..................... 44 figure 39: tx processing in buffered mode .......... ...................... 45 figure 40: rx processing in buffered mode.......... ...................... 46 figure 41: uc connections in buffered mode ......... .................... 47 figure 42: packet mode conceptual view ............. ..................... 49 figure 43: fixed length packet format.............. ........................ 50 figure 44: variable length packet format........... ....................... 51 figure 45: crc implementation ...................... ........................... 53 figure 46: manchester encoding/decoding ............ .................... 54 figure 47: data whitening .......................... ................................ 54 figure 48: uc connections in packet mode ........... ..................... 55 figure 49: optimized rx cycle ...................... ............................. 67 figure 50: optimized tx cycle...................... .............................. 68 figure 51: tx hop cycle ............................ ................................. 69 figure 52: rx hop cycle............................ ................................. 70 figure 53: rx tx rx cycle .......................................... ....... 71 figure 54: por timing diagram...................... ........................... 72 figure 55: manual reset timing diagram............. ...................... 72 figure 56: reference design circuit schematic...... .................... 73 figure 57: reference designs stackup.............. ........................ 74 figure 58: reference design layout (top view) ...... .................... 74 figure 59: 915 mhz saw filter plot ................. .......................... 75 figure 60: 869 mhz saw filter plot ................. .......................... 75 figure 61: sensitivity across the 868 mhz band..... .................... 77 figure 62: sensitivity across the 915 mhz band..... .................... 77 figure 63: fsk sensitivity loss vs. lo drift....... ......................... 78 figure 64: ook sensitivity loss vs. lo drift....... ........................ 78 figure 65: fsk sensitivity vs. rx bw ............... .......................... 79 figure 66: ook sensitivity change vs. rx bw ........ ................... 79 figure 67: sensitivity stability ................... .................................. 80 figure 68: fsk sensitivity vs. br .................. ............................. 80 figure 69: ook sensitivity vs. br .................. ............................ 81 figure 70: acr in fsk mode......................... ............................. 81 figure 71: acr in ook mode......................... ............................ 82 figure 72: pout for 869 mhz band operation ......... .................... 82 figure 73: pout for 915 mhz band operation ......... .................... 83 figure 74: pout and idd at all pa settings, 869 mhz ................. 83 figure 75: pout and idd at all pa settings, 915 mhz ................. 84 figure 76: pout stability.......................... .................................... 84 figure 77: 869 mhz spectral purity dc-1ghz ......... ................... 85 figure 78: 869 mhz spectral purity 1-6ghz .......... ..................... 85 figure 79: ook spectrum - 2kbps.................... .......................... 86 figure 80: ook spectrum - 8kbps.................... .......................... 86 figure 81: ook spectrum - 16.7kbps ................. ........................ 86 figure 82: fsk - 1.56kbps - +/-33 khz.............. .......................... 87 figure 83: fsk - 25 kbps - +/-50 khz............... ........................... 87 figure 84: fsk - 40 kbps - +/-40 khz............... ........................... 87 figure 85: dts 6db bandwidth....................... ............................ 88 figure 86: dts power spectral density.............. ........................ 88 figure 87: idd vs. temp and vdd.................... .......................... 89 figure 88: package outline drawing................. .......................... 90 figure 89: pcb land pattern........................ .............................. 90 figure 90: tape & reel dimensions .................. ......................... 91
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 4 of 92 www.semtech.com index of tables table 1: ordering information...................... ................................. 1 table 2: SX1211 pinouts............................ .................................. 7 table 3: absolute maximum ratings .................. .......................... 8 table 4: operating range ........................... ................................. 8 table 5: power consumption specification........... ........................ 8 table 6: frequency synthesizer specification ....... ....................... 9 table 7: transmitter specification ................. ............................... 9 table 8: receiver specification .................... .............................. 10 table 9: digital specification ..................... ................................. 11 table 10: mcparam_freq_band setting................ ..................... 15 table 11: pa rise/fall times ....................... .............................. 20 table 12: operating modes .......................... .............................. 33 table 13: pin configuration vs. chip mode.......... ....................... 33 table 14: data operation mode selection ............ ...................... 35 table 15: config vs. data spi interface selection .. .................... 36 table 16: status of fifo when switching between dif ferent modes of the chip .................................. .................................... 39 table 17: interrupt mapping in continuous rx mode .. ................ 42 table 18: interrupt mapping in continuous tx mode.. ................. 42 table 19: relevant config. registers in continuous mode ........ 43 table 20: interrupt mapping in buffered rx and stby modes ...... 46 table 21: interrupt mapping in buffered tx mode .... ................... 46 table 22: relevant configuration registers in buffe red mode .... 47 table 23: interrupt mapping in rx and stby in packe t mode ....... 55 table 24: interrupt mapping in tx packet mode...... .................... 55 table 25: relevant configuration registers in packe t mode....... 56 table 26: registers list ........................... ................................... 58 table 27: mcparam register description ............. ...................... 58 table 28: irqparam register description ............ ...................... 60 table 29: rxparam register description............. ....................... 62 table 30: syncparam register description........... .................... 63 table 31: txparam register description ............. ....................... 64 table 32: oscparam register description............ ..................... 64 table 33: pktparam register description............ ...................... 65 table 34: crystal resonator specification .......... ........................ 66 table 35: reference design bom ..................... ......................... 74 table 36: tools ordering information............... ........................... 75 table 37: fsk rx filters vs. bit rate.............. ............................ 76 table 38: ook rx filters vs. bit rate.............. ........................... 76 acronyms bom bill of materials br bit rate bw bandwidth ccitt comit consultatif international tlphonique et tlgraphique - itu cp charge pump crc cyclic redundancy check dac digital to analog converter dds direct digital synthesis dll dynamically linked library erp equivalent radiated power etsi european telecommunications standards institute fcc federal communications commission fdev frequency deviation fifo first in first out fs frequency synthesizer fsk frequency shift keying gui graphical user interface ic integrated circuit id identificator if intermediate frequency irq interrupt request itu international telecommunication union lfsr linear feedback shift register lna low noise amplifier lo local oscillator lsb least significant bit msb most significant bit nrz non return to zero nzif near zero intermediate frequency ook on off keying pa power amplifier pcb printed circuit board pfd phase frequency detector pll phase-locked loop por power on reset rbw resolution bandwidth rf radio frequency rssi received signal strength indicator rx receiver saw surface acoustic wave spi serial peripheral interface sr shift register stby standby tx transmitter uc microcontroller vco voltage controlled oscillator xo crystal oscillator xor exclusive or
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 5 of 92 www.semtech.com this product datasheet contains a detailed descript ion of the SX1211 performance and functionality. pl ease consult the semtech website for the latest updates or errat a. 1. general description the SX1211 is a single chip fsk and ook transceiver capable of operation in the 863-870 mhz and 902-92 8 mhz license free ism frequency bands, as well as the 95 0 - 960 mhz frequency band. it complies with both t he relevant european and north american standards, en 300-220 v 2.1.1 (june 2006 release) and fcc part 15 (10-1-200 6 edition). a unique feature of this circuit is its e xtremely low current consumption in receiver mode o f only 3ma (typ). the SX1211 comes in a 5x5 mm tqfn-32 package. 1.1. simplified block diagram figure 1: SX1211 simplified block diagram
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 6 of 92 www.semtech.com 1.2. pin diagram the following diagram shows the pins arrangement of the qfn package, top view. figure 2: SX1211 pin diagram notes: yyww refers to the date code ------ refers to the lot number
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 7 of 92 www.semtech.com 1.3. pin description table 2: SX1211 pinouts number name type description 0 gnd i exposed ground pad 1 test5 i/o connect to gnd 2 test1 i/o connect to gnd 3 vr_vco o regulated supply of the vco 4 vco_m i/o vco tank 5 vco_p i/o vco tank 6 lf_m i/o pll loop filter 7 lf_p i/o pll loop filter 8 test6 i/o connect to gnd 9 test7 i/o connect to gnd 10 xtal_p i/o crystal connection 11 xtal_m i/o crystal connection 12 test0 i connect to gnd 13 test8 i/o por. do not connect if unused 14 nss_config i spi config enable 15 nss_data i spi data enable 16 miso o spi data output 17 mosi i spi data input 18 sck i spi clock input 19 clkout o clock output 20 data i/o nrz data input and output (continuous m ode) 21 irq_0 o interrupt output 22 irq_1 o interrupt output 23 pll_lock o pll lock detection output 24 test2 i/o connect to gnd 25 test3 i/o connect to gnd 26 vdd i supply voltage 27 vr_1v o regulated supply of the analog circuitry 28 vr_dig o regulated supply of digital circuitry 29 vr_pa o regulated supply of the pa 30 test4 i/o connect to gnd 31 rfio i/o rf input/output 32 nc - connect to gnd note: pin 13 (test 8) can be used as an manual rese t trigger. see section 7.4.2 for details on its use .
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 8 of 92 www.semtech.com 2. electrical characteristics 2.1. esd notice the SX1211 is a high performance radio frequency de vice. it satisfies: class 2 of the jedec standard jesd22-a114-b (human body model), except on pins 3-4-5-27-28-29-31 where it satisfies class 1a. class iii of the jedec standard jesd22-c101c (char ged device model) on all pins. it should thus be handled with all the necessary es d precautions to avoid any permanent damage. 2.2. absolute maximum ratings stresses above the values listed below may cause pe rmanent device failure. exposure to absolute maximu m ratings for extended periods may affect device reli ability. table 3: absolute maximum ratings 2.3. operating range table 4: operating range 2.4. chip specification conditions: temp = 25 c, vdd = 3.3 v, crystal freq uency = 12.8 mhz, carrier frequency = 869 or 915 mh z, modulation fsk, data rate = 25 kb/s, fdev = 50 khz, fc = 100 khz, unless otherwise specified. 2.4.1. power consumption table 5: power consumption specification symbol description conditions min typ max unit iddsl supply current, sleep mode - 0.1 2 a iddst supply current in standby mode, clkout disabled crystal oscillator running (2) - 65 80 a iddfs supply current in fs mode frequency synthesizer running - 1.3 1.7 ma iddr supply current in rx mode - 3.0 3.5 ma iddt supply current in tx mode output power = +10 dbm output power = 1dbm (1) - - 25 16 30 21 ma ma (1) guaranteed by design and characterization (2) crystal cload=10pf, c0=2.5pf, rm=15 ohms symbol description min max unit vddmr supply voltage -0.3 3.7 v tmr storage temperature -55 125 c pmr input level - 0 dbm symbol description min max unit vddop supply voltage 2.1 3.6 v trop temperature -40 +85 c ml input level - 0 dbm
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 9 of 92 www.semtech.com 2.4.2. frequency synthesis table 6: frequency synthesizer specification (1) guaranteed by design and characterization 2.4.3. transmitter table 7: transmitter specification (1) guaranteed by design and characterization symbol description conditions min typ max unit fr frequency ranges programmable but requires specific bom 863 902 950 - - - 870 928 960 mhz mhz mhz br_f bit rate (fsk) nrz 1.56 - 200 kb/s br_o bit rate (ook) nrz 1.56 - 32 kb/s fda frequency deviation (fsk) 33 50 200 khz xtal crystal oscillator frequency 9 12.8 15 mhz fstep frequency synthesizer step variable, depending on the frequency. - 2 - khz ts_osc oscillator wake-up time from sleep mode (1) - 1.5 5 ms ts_fs frequency synthesizer wake-up time at most 10 khz away from the target from stby mode - 500 800 s 200 khz step - 180 - s 1 mhz step - 200 - s 5 mhz step - 250 - s 7 mhz step - 260 - s 12 mhz step - 290 - s 20 mhz step - 320 - s ts_hop frequency synthesizer hop time at most 10 khz away from the target 27 mhz step - 340 - s symbol description conditions min typ max unit maximum power setting - +12.5 - dbm rfop rf output power, programmable with 8 steps of typ. 3db minimum power setting - -8.5 - dbm pn phase noise measured with a 600 khz offset, at the transmitter output. - -112 - dbc/hz spt transmitted spurious at any offset between 200 khz and 600 khz, unmodulated carrier, fdev = 50 khz. - - -47 dbc ts_tr (1) transmitter wake-up time from fs to tx ready. - 12 0 500 s ts_tr2 (1) transmitter wake-up time from stby to tx ready. - 600 900 s
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 10 of 92 www.semtech.com 2.4.4. receiver on the following table, fc and fo describe the band width of the active channel filters as described in section 3.4.4.2. all sensitivities are measured receiving a pn15 seq uence, for a ber of 0.1.% table 8: receiver specification symbol description conditions min typ max unit 869 mhz, br=25 kb/s, fdev =50 khz, fc=100 khz - -107 - dbm 869 mhz, br=66.7 kb/s, fdev=100 khz, fc=200 khz - -103 - dbm 915 mhz, br=25 kb/s, fdev=50 khz, fc=100 khz - -105 - dbm rfs_f sensitivity (fsk) 915 mhz, br = 66.7 kb/s, fdev=100 khz, fc=200 khz - -101 - dbm 869 mhz, 2kb/s nrz fc-fo=50 khz, fo=50 khz - -113 - dbm 869 mhz, 16.7 kb/s nrz fc-fo=100 khz, fo=100 khz - -106 - dbm 915 mhz, 2kb/s nrz fc-fo=50 khz, fo=50 khz - -111 - dbm rfs_o sensitivity (ook) 915 mhz, 16.7 kb/s nrz fc-fo=100 khz, fo=100 khz - -105 - dbm ccr co-channel rejection modulation as wanted signa l - -12 - dbc offset = 300 khz, unwanted tone is not modulated - 27 - db offset = 600 khz, unwanted tone is not modulated - 52 - db acr adjacent channel rejection offset = 1.2 mhz, unwanted tone is not modulated - 57 - db offset = 1 mhz, unmodulated - -48 - dbm offset = 2 mhz, unmodulated, no saw - -37 - dbm bi blocking immunity offset = 10 mhz, unmodulated, no saw - -33 - dbm rxbw_f (1,2) receiver bandwidth in fsk mode single side bw polyphase off 50 - 250 khz rxbw_o (1,2) receiver bandwidth in ook mode single side bw polyphase on 50 - 400 khz iip3 input 3 rd order intercept point interferers at 1mhz and 1.950 mhz offset - -28 - dbm ts_re (1) receiver wake-up time from fs to rx ready - 280 50 0 s ts_re2 (1) receiver wake-up time from stby to rx ready - 600 900 s 200 khz step - 400 - s 1mhz step - 400 - s 5mhz step - 460 - s 7mhz step - 480 - s 12mhz step - 520 - s 20mhz step - 550 - s ts_re_hop receiver hop time from rx ready to rx ready with a frequency hop 27mhz step - 600 - s ts_rssi rssi sampling time from rx ready - - 1/fdev s dr_rssi rssi dynamic range ranging from sensitivity - 70 - db (1) guaranteed by design and characterization (2) this reflects the whole receiver bandwidth, as des cribed in sections 3.4.4.1 and 3.4.4.2
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 11 of 92 www.semtech.com 2.4.5. digital specification conditions: temp = 25 c, vdd = 3.3 v, crystal freq uency = 12.8 mhz, unless otherwise specified. table 9: digital specification note: on pin 10 (xtal_p) and 11 (xtal_n), maximum v oltages of 1.8v can be applied. symbol description conditions min typ max unit vih digital input level high 0.8*vdd - - v vil digital input level low - - 0.2*vdd v voh digital output level high imax=1ma 0.9*vdd - - v vol digital output level low imax=-1ma - - 0.1*vdd v sck_config spi config. clock frequency - - 6 mhz sck_data spi data clock frequency - - 1 mhz t_data data hold and setup time 2 - - s t_mosi_c mosi setup time for spi config. 250 - - n s t_mosi_d mosi setup time for spi data. 312 - - ns t_nssc_l nss_config low to sck rising edge. sck falling edge to nss_config high. 500 - - ns t_nssd_l nss_data low to sck rising edge. sck falling edge to nss_data high. 625 - - ns t_nssc_h nss_config rising to falling edge. 500 - - ns t_nssd_h nss_data rising to falling edge. 625 - - ns
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 12 of 92 www.semtech.com 3. architecture description this section describes in depth the architecture of this ultra low-power transceiver: waveform generator fsk demod bitsync ook demod control xo rssi lo1 rx lo2 rx i i q q lo1 tx i q lo2 tx lo1 rx lo2 rx lo1 tx lo2 tx lo2 tx rfio xtal_p xtal_m vr_vco vr_pa irq_0 irq_1 mosi miso sck nss_config clkout data nss_data test(8:0) vco_p vco_m lf_p lf_m vr_dig pll_lock pa lna i q q i i q lo generator frequency synthesizer vr_1v figure 3: SX1211 detailed block diagram 3.1. power supply strategy to provide stable sensitivity and linearity charact eristics over a wide supply range, the SX1211 is in ternally regulated. this internal regulated power supply str ucture is described below:
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 13 of 92 www.semtech.com vdd C pin 26 2.1 C 3.6v external supply reg_top 1.4 v reg_dig 1.0 v reg_vco 0.85 v reg_pa 1.80 v vr_vco pin 3 vr_pa pin 29 biasing : -pa driver -pa choke (ext) biasing : -vco circuit -ext. vco tank biasing digital blocks vr_dig pin 28 biasing analog blocks vr_1v pin 27 reg_ana 1.0 v biasing : -spi -config. registers -por 1 ? f y5v 1 ? f y5v 220nf x7r 100nf x7r 47nf x7r vbat figure 4: power supply breakdown to ensure correct operation of the regulator circui t, the decoupling capacitor connection shown in fig ure 4 is required. these decoupling components are recommend ed for any design. 3.2. frequency synthesis description the frequency synthesizer of the SX1211 is a fully integrated integer-n type pll. the pll circuit requ ires only five external components for the pll loop filter and the vco tank circuit. 3.2.1. reference oscillator the SX1211 embeds a crystal oscillator, which provi des the reference frequency for the pll. the recomm ended crystal specification is given in section 7.1. 3.2.2. clkout output the reference frequency, or a sub-multiple of it, c an be provided on clkout (pin 19) by activating the bit oscparam_clkout_on. the division ratio is programme d through bits oscparam_clkout_freq. the two applications of the clkout output are: to provide a clock output for a companion uc, thus saving the cost of an additional oscillator. clkou t can be made available in any operation mode, except sleep mode, and is automatically enabled at power-up. to provide an oscillator reference output. measure ment of the clkout signal enables simple software trimming of the initial crystal tolerance. note: to minimize the current consumption of the sx 1211, ensure that the clkout signal is disabled whe n unused.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 14 of 92 www.semtech.com 3.2.3. pll architecture the crystal oscillator (xo) forms the reference osc illator of an integer-n phase locked loop (pll), wh ose operation is discussed in the following section. fi gure 5 shows a block schematic of the SX1211 pll. h ere the crystal reference frequency and the software contro lled dividers r, p and s determine the output frequ ency of the pll. pfd 75.(p i +1)+s i xo (r i +1) vr_vco xt_m xt_p lf_m lf_p vco_m vco_p lo vtune fcomp figure 5: frequency synthesizer description the vco tank inductors are connected on an external differential input. similarly, the loop filter is also located externally. however, there is an internal 8pf capac itance at vco input that should be subtracted from the desired loop filter capacitance. the output signal of the vco is used as the input t o the local oscillator (lo) generator stage, illust rated in figure 6. the vco frequency is subdivided and used in a serie s of up (down) conversions for transmission (recept ion). lo vco output receiver los transmitter los lo1 rx lo2 rx 8 90 i q lo1 tx 90 i q lo2 tx 8 90 i q figure 6: lo generator 3.2.4. pll tradeoffs with an integer-n pll architecture, the following c riterion must be met to ensure correct operation: the comparison frequency, fcomp, of the phase freq uency detector (pfd) input must remain higher than six times the pll bandwidth (pllbw) to guarantee loop s tability and to reject harmonics of the comparison frequency fcomp. this is expressed in the inequalit y: 6 fcomp pllbw however the pllbw has to be sufficiently high to a llow adequate pll lock times because the divider ration r determines fcomp, it should be set close to 119, leading to fcomp 100 khz which will ensure suitable pll stability and speed.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 15 of 92 www.semtech.com with the recommended bill of materials (bom) of the reference design of section 7.5.3, the pll prototy pe is the following: 64 r 169 s < p+1 pllbw = 15 khz nominal startup times and reference frequency spurs as spe cified. 3.2.5. voltage controlled oscillator the integrated vco requires only two external tank circuit inductors. as the input is differential, th e two inductors should have the same nominal value. the performance of these components is important for both the phas e noise and the power consumption of the pll. it is recomme nded that a pair of high q factor inductors is sele cted. these should be mounted orthogonally to other inductors ( in particular the pa choke) to reduce spurious coup ling between the pa and vco. in addition, such measures may reduce radiated pulling effects and undesirable transient behavior, thus minimizing spectral occupa ncy. note that ensuring a symmetrical layout of the vco inductors will further improve pll spectral purity. for best performance wound type inductors, with tig ht tolerance, should be used as described in sectio n 7.5.3. 3.2.5.1. sw settings of the vco to guarantee the optimum operation of the vco over the SX1211s frequency and temperature ranges, the following settings should be programmed into the sx 1211: target channel (mhz) 863- 870 902- 915 915- 928 950- 960 freq_band 10 00 01 10 table 10: mcparam_freq_band setting 3.2.5.2. trimming the vco tank by hardware and soft ware to ensure that the frequency band of operation may be accurately addressed by the r, p and s dividers of the synthesizer, it is necessary to ensure that the vco is correctly centered. note that for the reference design (see section 7.5) no centering is necessary. however, an y deviation from the reference design may require t he optimization procedure, outlined below, to be imple mented. this procedure is simplified thanks to the built-in vco trimming feature which is controlled over the spi i nterface. this tuning does not require any rf test equipment, and can be achieved by simply measuring vtune, the voltage between pins 6 (lfm) and 7 (lfp). the vco is centered if the voltage is within the ra nge: 150 ) ( 50 mv vtune note that this measurement should be conducted when in transmit mode at the center frequency of the de sired band (for example ~867 mhz in the 863-870 mhz band) , with the appropriate mcparam_freq_band setting. if this inequality is not satisfied then adjust the mcparam_vco_trim bits from 00 whilst monitoring vt une. this allows the vco voltage to be trimmed in + 60 mv inc rements. should the desired voltage range be inacce ssible, the voltage may be adjusted further by changing the tank circuit inductance value. note that an increa se in inductance will result in an increase vtune.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 16 of 92 www.semtech.com note for mass production: the vco capacitance is piece to piece dependant. a s such, the optimization proposed above should be verified on several prototypes, to ensure that the population is centered on 100 mv. 3.2.6. pll loop filter to adequately reject spurious components arising fr om the comparison frequency fcomp, an external 2 nd order loop filter is employed. lf_m cl1 cl2 lf_p rl1 figure 7: loop filter following the recommendations made in section 3.2.4 , the loop filter proposed in the reference design s bill of material on section 7.5.3 should be used. the loop filter settings are frequency band independent and are hence relevant to all implementations of the SX1211. 3.2.7. pll lock detection indicator the SX1211 also features a pll lock detect indicato r. this is useful for optimizing power consumption, by adjusting the synthesizer wake up time (ts_fs), since the pll startup time is lower than specified under nominal conditions. the lock status can be read on bit irqparam_pll_loc k, and must be cleared by writing a 1 to this sam e register. in addition, the lock status can be reflected in pi n 23 pll_lock, by setting the bit irqparam_enable_l ock_detect. 3.2.8. frequency calculation as shown in figure 5 the pll structure comprises th ree different dividers, r, p and s, which set the o utput frequency through the lo. a second set of dividers is also available to allow rapid switching between a pair of frequencies: r1/p1/s1 and r2/p2/s2. these six divid ers are programmed by six bytes of the register mcp aram from addresses 6 to 11. 3.2.8.1. fsk mode the following formula gives the relationship betwee n the local oscillator, and r, p and s values, when using fsk modulation. ( ) [ ] s p r fxtal fsk frf flo fsk frf + + + = = )1 75 1 8 9 , 8 9 , 3.2.8.2. ook mode due to the manner in which the baseband ook symbols are generated, the signal is always offset by the fsk frequency deviation (fdev - as programmed in mcpara m_freq_dev). hence, the center of the transmitted o ok signal is:
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 17 of 92 www.semtech.com ( ) [ ] fdev s p r fxtal tx ook frf fdev flo tx ook frf - + + + = - = )1 75 1 8 9 , , 8 9 , , consequently, in receive mode, due to the low inter mediate frequency (low-if) architecture of the sx12 11 the frequency should be configured so as to ensure the correct low-if receiver baseband center frequency, if2. ( ) [ ] 2 )1 75 1 8 9 , , 2 8 9 , , if s p r fxtal rx ook frf if flo rx ook frf - + + + = - = note that from section 3.4.4, it is recommended tha t if2 be set to 100 khz.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 18 of 92 www.semtech.com 3.3. transmitter description the SX1211 is set to transmit mode when mcparam_chi p_mode = 100. waveform generator lo1 tx lo2 tx lo2 tx rfio pa i q q i i q dds dacs interpolation filters baseband if rf data clock first up - conversion second up-conversion amplification figure 8: transmitter architecture 3.3.1. architecture description the baseband i and q signals are digitally generate d by a dds whose digital to analog converters (dac) followed by two anti-aliasing low-pass filters transform the digital signal into analog in-phase (i) and quadra ture (q) components whose frequency is the selected frequenc y deviation (fdev). i(t) q(t) fdev 1 figure 9: i(t), q(t) overview in fsk mode, the relative phase of i and q is switc hed by the input data between -90 and +90 with co ntinuous phase. the modulation is therefore performed at thi s initial stage, since the information contained in the phase difference will be converted into a frequency shift when the i and q signals are up-converted in the f irst mixer stage. this first up-conversion stage is duplicated to enhance image rejection. the fsk convention is such that: fdev frf data fdev frf data - ? = + ? = ''0'' ''1''
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 19 of 92 www.semtech.com in ook mode, the phase difference between the i and q channels is kept constant (independent of the tr ansmitted data). thus, the first stage of up-conversion creat es a fixed frequency signal at the low if = fdev (t his explains why the transmitted ook spectrum is offset by fdev) . ook modulation is accomplished by switching on and off the pa and pa regulator stages. by convention: paoff data paon data ? = ? = ''0'' ''1'' after the interpolation filters, a set of four mixe rs combines the i and q signals and converts them i nto a pair of complex signals at the second intermediate frequenc y, equal to 1/8 of the lo frequency, or 1/9 of the rf frequency. these two new i and q signals are then c ombined and up-converted to the final rf frequency by two quadrature mixers fed by the lo signal. the signal is pre-amplified, and then the transmitter output i s driven by a final power amplifier stage. 3.3.2. bit rate setting in continuous transmit mode, setting the bit rate i s useful to determine the frequency of dclk. as exp lained in section 5.3.2, dclk will trigger an interrupt on th e uc each time a new bit has to be transmitted. [ ] ) _ ( 1 * 64 br mcparam val f br xtal + = 3.3.3. alternative settings bit rate, frequency deviation and tx interpolation filter settings are a function of the reference osc illator crystal frequency, f xtal . settings other than those programmable with a 12. 8 mhz crystal can be obtained by selection of the correct reference oscillator frequency. please contact your local semtech representative for furth er details. 3.3.4. fdev setting in fsk mode the frequency deviation, fdev, of the fsk transmitt er is programmed through bits mcparam_freq_dev: [ ] ) _ _ ( 1 * 32 dev freq mcparam val f fdev xtal + = for correct operation the modulation index ? should be such that: 2 * 2 3 = br fdev b it should be noted that for communications between a pair of SX1211s, that fdev should be at least 33 khz to ensure a correct operation on the receiver side. 3.3.5. fdev setting in ook mode fdev has no physical meaning in ook transmit mode. however, as has been shown - due to the dds baseban d signal generation, the ook signal is always offset by -fdev (see formulas is section 3.2.8). it is s uggested that fdev retains its default value of 100 khz in ook mo de.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 20 of 92 www.semtech.com 3.3.6. interpolation filter after digital to analog conversion, both i and q si gnals are smoothed by interpolation filters. this b lock low-pass filters the digitally generated signal, and prevent s the alias signals from entering the modulators. i ts bandwidth can be programmed with the register rxparam_interpfiltt x, and should be set to: ?? ? ?? ? + @ 2 * 3 br fdev bw where fdev is the programmed frequency deviation as set in mcparam_freq_dev, and br is the physical bi t rate of transmission. notes: low interpolation filter bandwidth will attenuate the baseband i/q signals thus reducing the power of the fsk signal. conversely, excessive bandwidth will degrad e spectral purity. for the wideband fsk modulation, for example when operating in dts mode, the recommended filter setti ng can not be reached. however, the impact upon spectr al purity will be negligible, due to the already wi deband channel. 3.3.7. power amplifier the power amplifier (pa) integrated in the SX1211 o perates under a regulated voltage supply of 1.8 v. the external pa choke inductor is biased by an internal regulator output made available on pin 29 (vr_pa). thanks to these features, the pa output power is consistent o ver the power supply range. this is important for m obile applications where this allows both predictable rf performance and battery life. 3.3.7.1. rise and fall times control in ook mode, the pa ramp times can be accurately co ntrolled through the mcparam_pa_ramp register. thos e bits directly control the slew rate of vr_pa output (pin 29). table 11: pa rise/fall times mcparam_pa_ramp t vr_pa t pa_out (rise / fall) 00 3 us 2.5 / 2 us 01 8.5 us 5 / 3 us 10 15 us 10 / 6 us 11 23 us 20 / 10 us
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 21 of 92 www.semtech.com data vr_pa [v] 95 % t vr_pa t vr_pa 95 % 60 db 60 db pa out put power t pa_out t pa_out figure 10: pa control 3.3.7.2. optimum load impedance as the pa and the lna front-ends in the SX1211 shar e the same input/output pin, they are internally ma tched to approximately 50 . pmax-1db circle pmax-1db circle pmax-1db circle pmax-1db circle max power max power max power max power zopt = 30+j25 zopt = 30+j25 zopt = 30+j25 zopt = 30+j25 figure 11: optimal load impedance chart please refer to the reference design section for an optimized pa load setting.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 22 of 92 www.semtech.com 3.3.7.3. suggested pa biasing and matching the recommended pa bias and matching circuit is ill ustrated below: figure 12: recommended pa biasing and output matchi ng please refer to section 7.5.3 of this document for the optimized matching arrangement for each frequen cy band. 3.3.8. common input and output front-end the receiver and the transmitter share the same rfi o pin (pin 31). figure 13 below shows the configura tion of the common rf front-end. in transmit mode, the pa and the pa regulator are active, with the voltage on the vr_pa pin equal to the nominal voltage of the regulator (1.8 v). the exter nal inductance is used to bias the pa. in receive mode, both pa and pa regulator are off and vr_pa is tied to ground. the external inductanc e lt1 is then used to bias the lna. rfio vr_pa pa reg_pa rx_on lna to antenna figure 13: front-end description vr_pa rfio 100nh 47nf saw low-pass and dc block pa antenna port dc block
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 23 of 92 www.semtech.com 3.4. receiver description the SX1211 is set to receive mode when mcparam_chip _mode = 011. fsk demod bit synchronizer ook demod control logic -pattern recognition -fifo handler -spi interface -packet handler rssi lo1 rx lo2 rx lna baseband, if2 in ook if1 rf first down - conversion second down - conversion figure 14: receiver architecture 3.4.1. architecture the SX1211 receiver employs a super-heterodyne arch itecture. here, the first if is 1/9 th of the rf frequency (approximately 100mhz). the second down-conversion down-converts the i and q signals to base band in t he case of the fsk receiver (zero if) and to a low-if (if2) for the ook receiver. channel lo1 rx image frequency if1 100mhz first down - conversion second down - conversion 0 if2=0 in fsk mode frequencyl lo2 rx figure 15: fsk receiver setting channel lo1 rx image frequency if1 100mhz first down - conversion second down - conversion 0 if2<0 in fsk mode equal to fo lo2 rx frequency figure 16: ook receiver setting after the second down-conversion stage, the receive d signal is channel-select filtered and amplified t o a level adequate for demodulation. both fsk and ook demodul ation are available. finally, an optional bit synch ronizer (bitsync) is provided, to be supply a synchronous c lock and data stream to a companion uc in continuou s mode,
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 24 of 92 www.semtech.com or to fill the fifo buffers with glitch-free data i n buffered mode. the operation of the receiver is n ow described in detail. note: image rejection is achieved by the saw filter . 3.4.2. lna and first mixer in receive mode, the rfio pin is connected to a fix ed gain, common-gate, low noise amplifier (lna). th e performance of this amplifier is such that the nois e figure (nf) of the receiver can be estimated to b e 7 db. 3.4.3. if gain and second i/q mixer following the lna and first down-conversion, there is an if amplifier whose gain can be programmed fro m - 13.5 db to 0 db in 4.5 db steps, via the register m cparam_if_gain. the default setting corresponds to 0 db gain, but lower values can be used to increase the rssi d ynamic range. refer to section 3.4.7 for additional information. 3.4.4. channel filters the second mixer stages are followed by the channel select filters. the channel select filters have a strong influence on the noise bandwidth and selectivity of the receiver and hence its sensitivity. each filte r comprises a passive and active section. 3.4.4.1. passive filter each channel select filter features a passive secon d-order rc filter, with a bandwidth programmable th rough the bits rxparam_passivefilt. as the wider of the two f ilters, its effect on the sensitivity is negligible , but its bandwidth has to be setup instead to optimize blocking immuni ty. the value entered into this register sets the s ingle side bandwidth of this filter. for optimum performance i t should be set to 3 to 4 times the cutoff frequenc y of the active butterworth (or polyphase) filter described in the next section. butterfilt filter passive t butterffil fc bw fc * 4 * 3 , 3.4.4.2. active filter the fine channel selection is performed by an act ive, third-order, butterworth filter, which acts as a low-pass filter for the zero-if configuration (fsk), or a complex p olyphase filter for the low-if (ook) configuration. the rxparam_polypfilt_on bit enables/disables the polyp hase filter. f c low-pass filter for fsk ( rxparam_polyfilt_on=0 ) polyphase filter for ook ( rxparam_polyfilt_on=1 ) - f c 0 f requency f requency 0 -f c -f o canceled side of the polyphase filter figure 17: active channel filter description
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 25 of 92 www.semtech.com as can be seen from figure 17, the required bandwid th of this filter varies between the two demodulati on modes. fsk mode: the 99% energy bandwidth of an fsk modul ated signal is approximated to be: ?? ? ?? ? + = 2 * 2 %, 99 br fdev bw fsk the bits rxparam_butterfilt set fc, the cutoff freq uency of the filter. as we are in a zero-if configu ration, the fsk lobes are centered around the virtual dc frequenc y. the choice of fc should be such that the modulat ed signal falls in the filter bandwidth, anticipating the loc al oscillator frequency drift over the operating te mperature and aging of the device: drifts fsk lo bw fc + > %, 99 * 2 please refer to the charts in section 3.4.5 for an accurate overview of the filter bandwidth vs. setti ng. ook mode: the 99% energy bandwidth of an ook modul ated signal is approximated to be: br tbit bw ook .2 2 %, 99 = = the bits rxparam_polypfilt_center set fo, the cente r frequency of the polyphase filter when activated. fo should always be chosen to be equal to the low intermediat e frequency of the receiver (if2). this is why, in the gui described in section 7.2.1 of this document, the lo w if frequency of the ook receiver denoted if2 has been replaced by fo. the following setting is recommended: " 0011 " _ 100 = = polypfilt rxparam khz fo the value stored in rxparam_butterfilt determines f c, the filter cut-off frequency. so the user should set fc according to: drifts ook lo bw fo fc + > - %, 99 ) (* 2 again, fc as a function of rxparam_butterfilt is gi ven in the section 3.4.6. 3.4.5. channel filters setting in fsk mode fc, the 3db cutoff frequency of the butterworth fil ter used in fsk reception, is programmed through th e bit rxparam_butterfilt. however, the whole receiver cha in influences this cutoff frequency. thus the chann el select and resultant filter bandwidths are summarized in t he following chart:
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 26 of 92 www.semtech.com butterworth filter's bw, fsk 0 50 100 150 200 250 300 350 400 450 0 2 4 6 8 10 12 14 16 val (rxparam_butterfilt) [d] fc (3db cutoff) [khz] actual bw theoretical bw figure 18: butterworth filter's actual bw table 37 suggests filter settings in fsk mode, alon g with the corresponding passive filter bandwidth a nd the accepted tolerance on the crystal reference. 3.4.6. channel filters setting in ook mode the center frequency, fo, is always set to 100khz. the following chart shows the receiver bandwidth wh en changing rxparam_butterfilt bits, whilst the polyph ase filter is activated. polyphase filter's bw, ook 0 50 100 150 200 250 300 350 400 450 0 2 4 6 8 10 12 14 16 val (rxparam_butterfilt [d] rxparam_polypfilt="0011" fc-fo with fo=100 khz [khz] actual bw theoretical bw figure 19: polyphase filter's actual bw table 38 suggests a few filter settings in ook mode , along with the corresponding passive filter bandw idth and the accepted tolerance on the crystal reference. 3.4.7. rssi after filtering, the in-phase and quadrature signal s are amplified by a chain of 11 amplifiers, each w ith 6db gain. the outputs of these amplifiers are used to evaluat e the received signal strength (rssi). 3.4.7.1. resolution and accuracy whilst the rssi resolution is 0.5 db, the absolute accuracy is not expected to be better than +/- 3db due to process and external component variation. higher accuracy w hilst performing absolute rssi measurements will re quire additional calibration. 3.4.7.2. acquisition time
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 27 of 92 www.semtech.com in ook mode, the rssi evaluates the signal strength by sampling i(t) and q(t) signals 16 times in each period of the chosen if2 frequency (refer to section 3.4.1). in fsk mode, the signals are sampled 16 times in ea ch fdev period, fdev being the frequency deviation of the c ompanion transmitter. an average is then performed over a sliding window of 16 samples. hence, the rssi outpu t register rxparam_rssi is updated 16 times in each fdev or if2 period. the following settings should be respected: fsk mode: ensure that the fdev parameter (as descr ibed in mcparam_fdev) remains consistent with the actual frequency deviation of the companion transmi tter. ook reception: ensure that the fdev parameter (as described in mcparam_fdev) is equal with the freque ncy of i(t) and q(t) signals, i.e. the second intermedi ate frequency, if2, of the receiver (note that this equals fo, the center frequency of the polyphase filter). 3.4.7.3. dynamic range the dynamic range of the rssi is over 70 db, extend ing from the nominal sensitivity level. the if gain setting available in mcparam_if_gain is used to achieve thi s dynamic range: rssi response 0 20 40 60 80 100 120 140 160 180 -120 -100 -80 -60 -40 -20 0 pin [dbm] rssi_val [0.5db/bit] if_gain=00 if_gain=01 if_gain=10 if_gain=11 figure 20: rssi dynamic range the rssi response versus input signal is independen t of the receiver filter bandwidth. however in the absence of any input signal, the minimum value directly reflec ts upon the noise floor of the receiver, which is d ependant on the filter bandwidth of the receiver. 3.4.7.4. rssi irq source the SX1211 can also be used to detect a rssi level above a pre-configured threshold. the threshold is set in irqparam_rssi_irq_thresh and the irq status stored in irqparam_rssi_irq (cleared by writing a 1). an interrupt can be mapped to the irq0 or irq1 pins via bits irqparam_rx_stby_irq0 or irqparam_rx_stby_irq1. figure 21 shows the timing d iagram of the rssi interrupt source, with irqparam_rssi_irq_thresh set to 28.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 28 of 92 www.semtech.com irqparam_rssi_irq clear interrupt 24 26 27 30 25 20 20 20 18 22 20 22 34 33 33 rxparam_rssi_val(7:0) figure 21: rssi irq timings 3.4.8. fdev setting in receive mode the effect of the fdev setting is different between fsk and ook modes: 3.4.8.1. fsk rx mode in fsk mode the fdev setting, as configured by mcpa ram_freq_dev, sets sampling frequencies on the rece iver. the user should make it consistent with the frequen cy deviation of the fsk signal that is received. 3.4.8.2. ook rx mode the frequency deviation fdev, as described above, s ets the sampling rate of the rssi block. it is ther efore necessary to set fdev to the recommended low-if fre quency, if2, of 100 khz: " 00000011 " _ _ 100 2 = = = dev freq mcparam khz if fdev 3.4.9. fsk demodulator the fsk demodulator provides data polarity informat ion, based on the relative phase of the input i and q signals at the baseband. its outputs can be fed to the bit syn chronizer to recover the timing information. the us er can also use the raw, unsynchronized, output of the fsk demo dulator in continuous mode. the fsk demodulator of the SX1211 operates most eff ectively for fsk signals with a modulation index gr eater than or equal to two: 2 * 2 3 = br fdev b 3.4.10. ook demodulator the ook demodulator performs a comparison of the rs si output and a threshold value. three different th reshold modes are available, programmed through the rxparam _ook_thresh_type register. the recommended mode of operation is the peak thr eshold mode, illustrated below in figure 22:
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 29 of 92 www.semtech.com zoom period as defined in rxparam_ook_thresh_dec_period decay in db as defined in rxparam_ook_thresh_step fixed 6db difference rssi (db) noise floor of receiver floor threshold defined by mcparam_ook_floor_thresh time peak -6db threshold zoom figure 22: ook demodulator description in peak threshold mode the comparison threshold lev el is the peak value of the rssi, reduced by 6db. i n the absence of an input signal or during the reception of a logical 0, the acquired peak value is decrem ented by one rxparam_ook_thresh_step every rxparam_ook_thresh_de c_period. when the rssi output is null for a long time (for i nstance after a long string of 0 received, or if no transmitter is present), the peak threshold level will continue fa lling until it reaches the floor threshold that i s programmed through the register mcparam_ook_floor_thresh. the default settings of the ook demodulator lead to the performance stated in the electrical specifica tion. however, in applications in which sudden signal dro ps are awaited during a reception, the three parame ters shall be optimized accordingly. 3.4.10.1. optimizing the floor threshold mcparam_ook_floor_thres determines the sensitivity of the ook receiver, as it sets the comparison thre shold for weak input signals (i.e. those close to the noise f loor). significant sensitivity improvements can be generated if configured correctly. note that the noise floor of the receiver at the de modulator input depends on: the noise figure of the receiver. the gain of the receive chain from antenna to base band. the matching - including saw filter. the bandwidth of the channel filters. it is therefore important to note that the setting of mcparam_ook_floor_thresh will be application dep endant. the following procedure is recommended to optimize mcpa ram_ook_floor_thresh.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 30 of 92 www.semtech.com set SX1211 in ook rx mode adjust bit rate, channel filter bw default rxparam_ook_thresh setting no input signal continuous mode optimization complete glitch activity on data ? monitor data pin (pin 20) increment mcparam_ook_floor_thres figure 23: floor threshold optimization the new floor threshold value found during this tes t should be the value used for ook reception with t hose receiver settings. note that if the output signal on data is logic 1 , the value of mcparam_ook_floor_thres is below the noise floor of the receiver chain. conversely, if the output si gnal on data is logic 1, the value of maparam_flo or_thres is several db above the noise floor. 3.4.10.2. optimizing ook demodulator response for f ast fading signals a sudden drop in signal strength can cause the bit error rate to increase. for applications where the expected signal drop can be estimated the following ook demo dulator parameters rxparam_ook_thresh_step and rxparam_ook_thresh_dec_period can be optimized as d escribed below for a given number of threshold decrements per bit rxparam_ook_thresh_dec_period: 000 once in each chip period (d) 001 once in 2 chip periods 010 once in 4 chip periods 011 once in 8 chip periods 100 twice in each chip period 101 4 times in each chip period 110 8 times in each chip period 111 16 times in each chip period for each decrement of rxparam_ook_thresh_step: 000 0.5 db (d) 001 1.0 db 010 1.5 db 011 2.0 db 100 3.0 db 101 4.0 db 110 5.0 db 111 6.0 db
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 31 of 92 www.semtech.com 3.4.10.3. alternative ook demodulator threshold mod es in addition to the peak ook threshold mode, the use r can alternatively select two other types of thres hold detectors: fixed threshold: the value is selected through the mcparam_ook_floor_thresh register (refer to sectio n 3.4.10.1 for further information concerning optimiz ation of the floor threshold). average threshold: data supplied by the rssi block is averaged with the following cutoff frequency: p * 8 00 _ _ br fcutoff cutoff ook rxparam = ? = p * 32 11 _ _ br fcutoff cutoff ook rxparam = ? = in the first example, the higher cut-off frequency enables a sequence of up to 8 consecutive 0 or 1 to be supported, whilst the lower cut-off frequency prese nted in the second example allows for the correct r eception of up to 32 consecutive 0 or 1. 3.4.11. bit synchronizer the bit synchronizer (bitsync) is a block that prov ides a clean and synchronized digital output, free of glitches. raw demodulator output (fsk or ook) dclk irq_1 data bitsync output to pin data and dclk in continuous mode figure 24: bitsync description the bitsync can be disabled through the bits rxpara m_bitsync_off, and by holding pin irq1 low. however , for optimum receiver performance, its use when running continuous mode is strongly advised. with this opti on a dclk signal is present on pin irq_1. the bitsync is automatically activated in buffered and packet modes. the bit synchronizer bit-rate is controlled by mcparam_br. for a given bit rate, this parameter is determined by: [ ] br mcparam f br xtal _ 1 * 64 + =
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 32 of 92 www.semtech.com for proper operation, the bit synchronizer must fir st receive three bytes of alternating logic value p reamble, i.e. 0101 sequences. after this startup phase, the ris ing edge of dclk signal is centered on the demodula ted bit. subsequent data transitions will preserve this cent ering. this has two implications: firstly, if the bit rates of transmitter and recei ver are known to be the same, the SX1211 will be ab le to receive an infinite unbalanced sequence (all 0s o r all 1s) with no restriction. if there is a difference in bit rate between tx an d rx, the amount of adjacent bits at the same level that the bitsync can withstand can be estimated as: br br ts numberofbi d = * 2 1 this implies approximately 6 consecutive unbalanced bytes when the bit rate precision is 1%, which is easily achievable (crystal tolerance is in the range of 50 to 100 ppm). 3.4.12. alternative settings bit synchronizer and active channel filter settings are a function of the reference oscillator crystal frequency, f xtal . settings other than those programmable with a 12.8 mhz crystal can be obtained by selection of the cor rect reference oscillator frequency. please contact your local semtech representative for further details. 3.4.13. data output after ook or fsk demodulation, the baseband signal is made available to the user on pin 20, data, when continuous mode is selected. in buffered and packet modes, the data is retrieved from the fifo through the spi interface.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 33 of 92 www.semtech.com 4. operating modes this section summarizes the settings for each opera ting mode of the SX1211, and explains the functiona lity available and the timing requirements for switching between modes. 4.1. modes of operation table 12: operating modes mode mcparam_chip_mode active blocks sleep 000 spi, por standby 001 spi, por, top regulator, digital regula tor, xo, clkout (if activated through oscparam_clkout) fs 010 same + vco regulator, all pll and lo generat ion blocks receive 011 same as fs mode + lna, first mixer, if amplifier, second mixer set, channel filters, baseband amplifiers and limiters, rssi, oo k or fsk demodulator, bitsync and all digital features if enabled transmit 100 same as fs mode + dds, interpolation f ilters, all up-conversion mixers, pa driver, pa and external vr_pa pin output for pa cho ke. 4.2. digital pin configuration vs. chip mode table 13 describes the state of the digital ios in each of the above described modes of operation, reg ardless of the data operating mode (continuous, buffered, or packe t). table 13: pin configuration vs. chip mode chip . mode pin sleep mode standby mode fs mode receive mode transmit mode comment nss_config input input input input input nss_config has the priority over nss_data nss_data input input input input input miso input input input input input output only if nss_config or nssdata=0 mosi input input input input input sck input input input input input irq_0 high-z output (1) output (1) output output irq_1 high-z output (1) output (1) output output data input input input output input clkout high-z output output output output pll_lock high-z output (2) output (2) output (2) ou tput (2) notes: (1): high-z if continuous mode is activated, else output (2): output if pll_lock_en = 1, else high-z (3): valid logic states must be applied to inputs at all times to avoid unwanted leakage currents
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 34 of 92 www.semtech.com 5. data processing 5.1. overview 5.1.1. block diagram figure 25, illustrates the SX1211 data processing c ircuit. its role is to interface the data to/from t he modulator/demodulator and the uc access points (spi , irq and data pins). it also controls all the conf iguration registers. the circuit contains several control blocks which a re described in the following paragraphs. control data config spi packet handler sync recog. data irq_0 irq_1 miso mosi sck nss_data rx tx tx/rx data SX1211 fifo (+sr) figure 25: SX1211s data processing conceptual view the SX1211 implements several data operation modes, each with their own data path through the data pro cessing section. depending on the data operation mode selec ted, some control blocks are active whilst others r emain disabled. 5.1.2. data operation modes the SX1211 has three different data operation modes selectable by the user: continuous mode : each bit transmitted or received is accessed in r eal time at the data pin. this mode may be used if adequate external signal processing is avai lable. buffered mode : each byte transmitted or received is stored in a fifo and accessed via the spi bus. uc processing overhead is hence significantly reduced compared to continuous mode operation. the packet length is unlimited. packet mode (recommended) : user only provides/retrieves payload bytes to/fro m the fifo. the packet is automatically built with preamble, sync word, and o ptional crc, dc free encoding and the reverse opera tion is performed in reception. the uc processing overhead is hence reduced further compared to buffered mode. the maximum payload length is limited to the maximu m fifo limit of 64 bytes
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 35 of 92 www.semtech.com table 14: data operation mode selection mcparam_data_mode data operation mode 00 continuous 01 buffered 1x packet each of these data operation modes is described ful ly in the following sections. 5.2. control block description 5.2.1. spi interface 5.2.1.1. overview as illustrated in the figure 26 below, the SX1211s spi interface consists of two sub blocks: spi config : used in all data operation modes to read and writ e the configuration registers which control all the parameters of the chip (operating mode, bit rate, e tc...) spi data : used in buffered and packet mode to write and rea d data bytes to and from the fifo. (fifo interrupts can be used to manage the fifo content.) spi data (slave) mosi miso sck spi config (slave) config. registers SX1211 nss_data c (master) nss_config nss_config mosi miso sck nss_data config. registers fifo figure 26: spi interface overview and uc connection s both interfaces are configured in slave mode whilst the uc is configured as the master. they have sepa rate selection pins (nss_config and nss_data) but share the remaining pins: sck (spi clock): clock signal provided by the uc mosi (master out slave in): data input signal prov ided by the uc miso (master in slave out): data output signal pro vided by the SX1211 as described below, only one interface can be selec ted at a time with nss_config having the priority:
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 36 of 92 www.semtech.com table 15: config vs. data spi interface selection nss_data nss_config spi interface 0 0 config 0 1 data 1 0 config 1 1 none the following paragraphs describe how to use each o f these interfaces. 5.2.1.2. spi config write register to write a value into a configuration register the timing diagram below should be carefully followed b y the uc. the registers new value is effective from the risi ng edge of nss_config. start a(4) a(3) a(2) a(1) d(7) d(6) d(5) d(4) d(3) d(2) d(1) d(0) x x x x x x x d(7) d(6) d(5) d(4) d(3) d(2) d(1) sck (in) mosi (in) miso (out) nss_config (in) rw a(0) address = a1 current value at address a1* * when writing the new value at address a1, the cur rent content of a1 can be read by the uc. (in)/(out) refers to SX1211 side new value at address a1 x hz (input) d(0) stop 1 5 4 3 2 6 9 8 7 10 11 12 13 14 15 16 hz (input) figure 27: write register sequence note that when writing more than one register succe ssively, it is not compulsory to toggle nss_config back high between two write sequences. the bytes are alternat ively considered as address and value. in this inst ance, all new values will become effective on rising edge of nss_config. read register to read the value of a configuration register the t iming diagram below should be carefully followed by the uc.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 37 of 92 www.semtech.com start a(4) a(3) a(2) a(1) x x x x x x x d(7) d(6) d(5) d(4) d(3) d(2) d(1) sck (in) mosi (in) miso (out) nss_config (in) rw a(0) address = a1 current value at address a1 x d(0) hz (input) stop 1 5 4 3 2 6 9 8 7 10 11 12 13 14 15 16 x x x x x x x x hz (input) figure 28: read register sequence note that when reading more than one register succe ssively, it is not compulsory to toggle nss_config back high between two read sequences. the bytes are alte rnatively considered as address and value. 5.2.1.3. spi data write byte (before/during tx) to write bytes into the fifo the timing diagram bel ow should be carefully followed by the uc. sck (in) mosi (in) miso (out) x d1(6) d1(5) d1(4) d1(3) d1(2) d1(1) d2(7) d2(6) d2 (5) d2(4) d2(3) d2(2) d2(1) d2(0) d1(0) d1(7) hz (input) hz (input) hz (input) nss_data (in) x x x x x x x x x x x x x x x x x 1 5 4 3 2 6 8 7 1 5 4 3 2 6 8 7 1 st byte written 2 nd byte written figure 29: write bytes sequence (ex: 2 bytes) note that it is compulsory to toggle nss_data back high between each byte written. the byte is pushed into the fifo on the rising edge of nss_data
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 38 of 92 www.semtech.com read byte (after/during rx) to read bytes from the fifo the timing diagram belo w should be carefully followed by the uc. sck (in) miso (out) d1(6) d1(5) d1(4) d1(3) d1(2) d1(1) d2(7) d2(6) d2(5) d2(4) d2(3) d2(2) d2(1) d2(0) d1(0) 1 st byte read d1(7) hz (input) hz (input) mosi (in) x x x x x x x x x x x x x x x x hz (input) nss_data (in) 1 5 4 3 2 6 8 7 1 5 4 3 2 6 8 7 2 nd byte read x figure 30: read bytes sequence (ex: 2 bytes) note that it is compulsory to toggle nss_data back high between each byte read. 5.2.2. fifo 5.2.2.1. overview and shift register (sr) in buffered and packet modes of operation, both dat a to be transmitted and that has been received are stored in a configurable fifo (first in first out) device. it i s accessed via the spi data interface and provides several interrupts for transfer management. the fifo is 1 byte (8 bits) wide hence it only perf orms byte (parallel) operations, whereas the demodu lator functions serially. a shift register is therefore e mployed to interface the two devices. in transmit m ode it takes bytes from the fifo and outputs them serially (msb first) at the programmed bit rate to the modulator. simil arly, in rx the shift register gets bit by bit data from the demodu lator and writes them byte by byte to the fifo. thi s is illustrated in figure below. data tx/rx 8 1 sr (8bits) byte0 byte1 fifo msb lsb figure 31: fifo and shift register (sr) 5.2.2.2. size selection the fifo width is programmable, to 16, 32, 48 or 64 bytes via mcparam_fifo_size
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 39 of 92 www.semtech.com 5.2.2.3. interrupt sources and flags all interrupt sources and flags are configured in t he irqparam section of the configuration register, with the exception of fifo_threshold : /fifoempty: /fifoempty interrupt source is low whe n byte 0, i.e. whole fifo, is empty. otherwise it i s high. note that when retrieving data from the fifo, /fifoempty is updated on nss_data falling edge, i.e. when /fifoempty is updated to low state the currently st arted read operation must be completed. in other wo rds, /fifoempty state must be checked after each read operation for a decision on the next one (/fifoempty = 1: more byte(s) to read; /fifoempty = 0: no more byte to read). write_byte: write_byte interrupt source goes high for 1 bit period each time a new byte is transferre d from the sr to the fifo (i.e. each time a new byte is receiv ed) fifofull: fifofull interrupt source is high when t he last fifo byte, i.e. the whole fifo, is full. ot herwise it is low. fifo_overrun_clr: fifo_overrun_clr flag is set whe n a new byte is written by the user (in tx or stand by modes) or the sr (in rx mode) while the fifo is already fu ll. data is lost and the flag should be cleared by writing a 1, note that the fifo will also be cleared. tx_done: tx_done interrupt source goes high when f ifo is empty and the srs last bit has been send to the modulator (i.e. the last bit of the packet has been sent). one bit period delay is required after the rising edge of tx_done to ensure correct rf transmission of the la st bit. in practice this may not require special ca re in the uc software due to irq processing time. fifo_threshold: fifo_threshold interrupt sources behavior depends on the running mode (tx, rx or stb y mode) and the threshold itself can be programmed via mcpa ram_fifo_thresh (b value). this behavior is illustr ated in figure 32. # of bytes in fifo irq source 0 1 b b+1 b+2 tx rx & stby figure 32: fifo threshold irq source behavior 5.2.2.4. fifo clearing table 16 below summarizes the status of the fifo wh en switching between different modes table 16: status of fifo when switching between dif ferent modes of the chip from to fifo status comments cleared in buffered mode, fifo cannot be written in stby before tx stby tx not cleared in packet mode, fifo can be written in stby before tx stby rx cleared rx tx cleared rx stby not cleared in packet & buffered modes fifo can be read in stby after rx tx rx cleared tx stby not cleared any sleep cleared
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 40 of 92 www.semtech.com 5.2.3. sync word recognition 5.2.3.1. overview sync word recognition (also called pattern recognit ion in previous products) is activated by setting rxparam_sync_on. the bit synchronizer must also be activated. the block behaves like a shift register; it continu ously compares the incoming data with its internall y programmed sync word and asserts the sync irq source on each o ccasion that a match is detected. this is illustrat ed in figure 33. rx data (nrz) dclk bit n-x = sync_value[x] bit n-1 = sync_value[1] bit n = sync_value[0] sync figure 33: sync word recognition during the comparison of the demodulated data, the first bit received is compared with bit 7 (msb) of byte at address 22 and the last bit received is compared wi th bit 0 (lsb) of the last byte whose address is de termined by the length of the sync word. when the programmed sync word is detected the user can assume that this incoming packet is for the nod e and can be processed accordingly. 5.2.3.2. configuration size: sync word size can be set to 8, 16, 24 or 32 bits via rxparam_sync_size. in packet mode this fi eld is also used for sync word generation in tx mode. error tolerance: the number of errors tolerated in the sync word recognition can be set to 0, 1, 2 or 3 via rxparam_sync_tol. value: the sync word value is configured in syncpa ram_sync_value. in packet mode this field is also u sed for sync word generation in tx mode. 5.2.4. packet handler the packet handler is the block used in packet mode . its functionality is fully described in section 5 .5. 5.2.5. control the control block configures and controls the full chips behavior according to the settings programme d in the configuration registers.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 41 of 92 www.semtech.com 5.3. continuous mode 5.3.1. general description as illustrated in figure 34, in continuous mode the nrz data to (from) the (de)modulator is directly a ccessed by the uc on the bidirectional data pin (20). the spi data, fifo and packet handler are thus inactive. control config spi sync recog. data irq_1(dclk) miso mosi sck nss_config rx tx/rx irq_0 datapath SX1211 data figure 34: continuous mode conceptual view 5.3.2. tx processing in tx mode, a synchronous data clock for an externa l uc is provided on irq_1 pin. its timing with resp ect to the data is illustrated in figure 35. data is internall y sampled on the rising edge of dclk so the uc can change logic state anytime outside the greyed out setup/hold zon e. the use of dclk is compulsory in fsk and optional i n ook. data (nrz) dclk t_data t_data figure 35: tx processing in continuous mode
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 42 of 92 www.semtech.com 5.3.3. rx processing if the bit synchronizer is disabled, the raw demodu lator output is made directly available on data pin and no dclk signal is provided. conversely, if the bit synchronizer is enabled, syn chronous cleaned data and clock are made available respectively on data and irq_1 pins. data is sampled on the risi ng edge of dclk and updated on the falling edge as illustrated in figure 36. data (nrz) dclk figure 36: rx processing in continuous mode note that in continuous mode it is always recommend ed to enable the bit synchronizer to clean the data signal even if the dclk signal is not used by the uc. (bit synchronizer is automatically enabled in buffered and packet mode). 5.3.4. interrupt signals mapping the tables below give the description of the interr upts available in continuous mode. rx_stby_irq_0 rx 00 (d) sync 01 rssi irq_0 1x - irq_1 dclk table 17: interrupt mapping in continuous rx mode note: in continuous mode, no interrupt is available in stby mode tx irq_0 - irq_1 dclk table 18: interrupt mapping in continuous tx mode
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 43 of 92 www.semtech.com 5.3.5. uc connections uc SX1211 irq_0 irq_1 (dclk) data nss_config sck mosi miso figure 37: uc connections in continuous mode note that some connections may not be needed depend ing on the application: irq_0: if sync and rssi interrupts are not used. i n this case, leave floating. irq_1: if the chip is never used in tx fsk mode (d clk connection is not compulsory in rx and tx ook modes). in this case, leave floating. miso: if no read register access is needed. in thi s case, pull-up to vdd through a 100 k resistor. in addition, nss_data pin (unused in continuous mod e) should be pulled-up to vdd through a 100 k resistor. please refer to table 13 for SX1211s pins configur ation 5.3.6. continuous mode example configure all data processing related registers li sted below appropriately. in this example we assume that both bit synchronizer and sync word recognition are on. table 19: relevant configuration registers in conti nuous mode (data processing related only) tx rx description mcparam data_mode_x x x defines data operation mode ( continuous) irqparam rx_stby_irq_0 x defines irq_0 source in rx mode sync_on x enables sync word recognition sync_size x defines sync word size rxparam sync_tol x defines the error tolerance on sync wor d recognition syncparam sync_value x defines sync word value tx mode: go to tx mode (and wait for tx to be ready, see fi gure 50) send all packets bits on data pin synchronously w ith dclk signal provided on irq_1 go to sleep mode rx mode: program rx interrupts: irq_0 mapped to sync (rx_st by_irq_0=00) and irq_1 mapped to dclk (bit synchronizer enabled) go to rx mode (note that rx is not ready immediate ly, see figure 49) wait for sync interrupt get all packet bits on data pin synchronously with dclk signal provided on irq_1 go to sleep mode
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 44 of 92 www.semtech.com 5.4. buffered mode 5.4.1. general description as illustrated in figure 38, for buffered mode oper ation the nrz data to (from) the (de)modulator is n ot directly accessed by the uc but stored in the fifo and acces sed via the spi data interface. this frees the uc f or other tasks between processing data from the SX1211, furt hermore it simplifies software development and redu ces uc performance requirements (speed, reactivity). note that in this mode the packet handler stays inactive . an important feature is also the ability to empty t he fifo in stby mode, ensuring low power consumptio n and adding greater software flexibility. control fifo (+sr) data config spi sync recog. irq_0 irq_1 miso mosi sck nss_data nss_config rx tx datapath SX1211 data figure 38: buffered mode conceptual view note that bit synchronizer is automatically enabled in buffered mode. the sync word recognition must b e enabled (rxparam_sync_on=1) independently of the fifo filli ng method selected (irqparam_fifo_fill_method). 5.4.2. tx processing after entering tx in buffered mode, the chip expect s the uc to write into the fifo, via the spi data i nterface, all the data bytes to be transmitted (preamble, sync word, payload...). actual transmission of first byte will start either when the fifo is not empty (i.e. first byte writte n by the uc) or when the fifo is full depending on bit irqparam_tx_start _irq_0. in buffered mode the packet length is not limited, i.e. as long as there are bytes inside the fifo the y are sent. when the last byte is transferred to the sr, /fifoe mpty irq source is asserted to warn the uc, at that time fifo can still be filled with additional bytes if needed . when the last bit of the last byte has left the sr (i.e. 8 bit periods later), the tx_done interrupt s ource is asserted and the user can exit tx mode after waiting at leas t 1 bit period from the last bit processed by modul ator.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 45 of 92 www.semtech.com if the transmitter is switched off (for example due to entering another chip mode) during transmission it will stop immediately, even if there is still unsent data. figure 39 illustrates tx processing with a 16 byte fifo depth and tx_start_irq_0=0. please note that i n this example the packet length is equal to fifo size, bu t this does not need to be the case, the uc can use the fifo interrupts anytime during tx to manage fifo content s and write additional bytes. b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b14 b15 b12 b13 b0 b1 fifo 0 15 data tx (from sr) start condition (cf. tx_start_irq_0) /fifoempty fifofull tx_done b5 b2 b3 b4 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 xxx xxx from spi data figure 39: tx processing in buffered mode (fifo siz e = 16, tx_start_irq_0=0) 5.4.3. rx processing after entering rx in buffered mode, the chip requir es the uc to retrieve the received data from the fi fo. the fifo will actually start being filled with received byte s either; when a sync word has been detected (in th is case only the bytes following the sync word are filled into the f ifo) or when the fifo_fill bit is asserted by the u ser - depending on the state of bit, irqparam_fifo_fill_method. in buffered mode, the packet length is not limited i.e. as long as fifo_fill is set, the received byte s are shifted into the fifo. the uc software must therefore manage the transfer of the fifo contents by interrupt and ensure recept ion of the correct number of bytes. (in this mode, even if the remote transmitter has stopped, the demodulator wi ll output random bits from noise) when the fifo is full, fifofull irq source is asser ted to alert the uc, that at that time, the fifo ca n still be unfilled without data loss. if the fifo is not unfilled, onc e the sr is also full (i.e. 8 bits periods later) f ifo_overrun_clr is asserted and srs content is lost. figure 40 illustrates an rx processing with a 16 by tes fifo size and fifo_fill_method=0. please note t hat in the illustrative example of section 5.4.6, the uc does not retrieve any byte from the fifo through spi dat a, causing overrun.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 46 of 92 www.semtech.com b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b14 b15 b12 b13 b16 sync preamble noisy data b0 b1 b5 b2 b3 b4 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 0 15 data rx (to sr) start condition (cf. fifo_fill_method) /fifoempty fifofull fifo_overrun_clr write_byte fifo figure 40: rx processing in buffered mode (fifo siz e=16, fifo_fill_method=0) 5.4.4. interrupt signals mapping the tables below describe the interrupts available in buffered mode. rx_stby_irq_x rx stby 00 (d) - - 01 write_byte - 10 /fifoempty /fifoempty irq_0 11 sync - 00 (d) - - 01 fifofull fifofull 10 rssi - irq_1 11 fifo_threshold fifo_threshold table 20: interrupt mapping in buffered rx and stby modes tx irq_0 /fifoempty tx_irq_1=0 (d) fifofull irq_1 tx_irq_1=1 tx_done table 21: interrupt mapping in buffered tx mode
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 47 of 92 www.semtech.com 5.4.5. uc connections uc sx 1211 irq_0 irq_1 nss_config sck mosi miso nss_data figure 41: uc connections in buffered mode note that depending upon the application, some uc c onnections may not be needed: irq_0: if none of the relevant irq sources are use d. in this case, leave floating. irq_1: if none of the relevant irq sources are use d. in this case, leave floating. miso: if no read register access is needed and the chip is used in tx mode only. in this case, pull u p to vdd through a 100 k resistor. in addition, data pin (unused in buffered mode) sho uld be pulled-up to vdd through a 100 k resistor. please refer to table 13 for the SX1211s pin confi guration. 5.4.6. buffered mode example configure all data processing related registers li sted below appropriately. in this example we assume sync word recognition is on and fifo_fill_method=0. tx rx description data_mode_x x x defines data operation mode ( buffered) fifo_size x x defines fifo size mcparam fifo_thresh x x defines fifo threshold rx_stby_irq_0 x defines irq_0 source in rx & stby modes rx_stby_irq_1 x defines irq_1 source in rx & stby modes tx_irq_1 x defines irq_1 source in tx mode fifo_fill_method x defines fifo filling method fifo_fill x controls fifo filling status irqparam tx_start_irq_0 x defines tx start condition and ir q_0 source sync_size x defines sync word size rxparam sync_tol x defines the error tolerance on sync wor d detection syncparam sync_value x defines sync word value table 22: relevant configuration registers in buffe red mode (data processing related only) tx mode: program tx start condition and irqs: start tx when fifo is not empty (tx_start_irq_0=1) and irq_1 map ped to tx_done (tx_irq_1=1) go to tx mode (and wait for tx to be ready, see fi gure 50)
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 48 of 92 www.semtech.com write packet bytes into fifo. tx starts when the f irst byte is written (tx_start_irq_0=1). we assume the fifo is being filled via spi data faster than being unfille d by sr. wait for tx_done interrupt (+1 bit period) go to sleep mode rx mode: program rx/stby interrupts: irq_0 mapped to /fifoe mpty (rx_stby_irq_0=10) and irq_1 mapped to fifo_threshold (rx_stby_irq_1=11). configure fifo_t hresh to an appropriate value (ex: to detect packet end if its length is known) go to rx mode (note that rx is not ready immediate ly, cf section 7.3.1). wait for fifo_threshold interrupt (i.e. sync word has been detected and fifo filled up to the defined threshold). if it is packet end, go to stby (srs content is l ost). read packet bytes from fifo until /fifoempty goes low (or correct number of bytes is read). go to sleep mode.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 49 of 92 www.semtech.com 5.5. packet mode 5.5.1. general description similar to buffered mode operation, in packet mode the nrz data to (from) the (de)modulator is not dir ectly accessed by the uc but stored in the fifo and acces sed via the spi data interface. in addition, the SX1211s packet handler performs s everal packet oriented tasks such as preamble and s ync word generation, crc calculation/check, whitening/dewhit ening of data, address filtering, etc. this simplif ies still further software and reduces uc overhead by performing thes e repetitive tasks within the rf chip itself. another important feature is ability to fill and em pty the fifo in stby mode, ensuring optimum power c onsumption and adding more flexibility for the software. control data config spi packet handler sync recog. irq_0 irq_1 miso mosi sck nss_data nss_config rx tx datapath SX1211 data fifo (+sr) figure 42: packet mode conceptual view note that bit synchronizer and sync word recognitio n are automatically enabled in packet mode. 5.5.2. packet format two types of packet formats are supported: fixed le ngth and variable length, selectable by the pktparam_pkt_format bit. the maximum size of the pa yload is limited by the size of the fifo selected ( 16, 32, 48 or 64 bytes). 5.5.2.1. fixed length packet format in applications where the packet length is fixed in advance, this mode of operation may be of interest to minimize rf overhead (no length byte field is required). all nodes, whether tx only, rx only, or tx/rx should b e programmed with the same packet length value. the length of the payload is set by the pktparam_pa yload_length register and is limited by the size of the fifo selected.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 50 of 92 www.semtech.com the length stored in this register relates only to the payload which includes the message and the opti onal address byte. in this mode, the payload must contain at lea st one byte, i.e. address or message byte. an illustration of a fixed length packet is shown i n figure 43. it contains the following fields: preamble (1010...). sync word (network id). optional address byte (node id). message data. optional 2-bytes crc checksum. message 0 to (fifo size) bytes address byte crc 2-bytes sync word 1 to 4 bytes preamble 1 to 4 bytes payload/fifo crc checksum calculation fields added by the packet handler in tx and proces sed and removed in rx optional user provided fields which are part of the payload message part of the payload optional dc free data coding figure 43: fixed length packet format 5.5.2.2. variable length packet format this mode is necessary in applications where the le ngth of the packet is not known in advance and can vary over time. it is then necessary for the transmitter to s end the length information together with each packe t in order for the receiver to operate properly. in this mode the length of the payload, indicated b y the length byte in figure 44, is given by the fir st byte of the fifo and is limited only by the width of the fifo s elected. note that the length byte itself is not in cluded in its calculation. in this mode, the payload must contain at least 2 bytes, i.e. length + address or message byte. an illustration of a variable length packet is show n in figure 44. it contains the following fields: preamble (1010...). sync word (network id). length byte optional address byte (node id). message data. optional 2-bytes crc checksum.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 51 of 92 www.semtech.com message 0 to (fifo size - 1) bytes address byte length byte crc 2 - bytes sync word 1 to 4 bytes preamble 1 to 4 bytes payload/fifo crc check sum calculation fields added by the packet handler in tx and proces sed and removed in rx optional user provided fields which are part of the payload message part of the payload optional dc free data coding length figure 44: variable length packet format 5.5.3. tx processing in tx mode the packet handler dynamically builds th e packet by performing the following operations on the payload available in the fifo: add a programmable number of preamble bytes add a programmable sync word optionally calculating crc over complete payload f ield (optional length byte + optional address byte + message) and appending the 2 bytes checksum. optional dc-free encoding of the data (manchester or whitening). only the payload (including optional address and le ngth fields) is to be provided by the user in the f ifo. assuming that the chip is already in tx mode then, depending on irqparam_tx_start_irq_0 bit, packet transmission (starting with programmed preamble) wi ll start either after the first byte is written int o the fifo (tx_start_irq_0=1) or after the number of bytes wri tten reaches the user defined threshold (tx_start_i rq_0=0). the fifo can also be fully or partially filled in stby mode via pktparam_fifo_stby_access. in this case, t he start condition will only be checked when entering tx mod e. at the end of the transmission (tx_done = 1), the u ser must explicitly exit tx mode if required. (e.g. back to stby) note that while in tx mode, before and after actual packet transmission (not enough bytes or tx_done), additional preamble bytes are automatically sent to the modula tor. when the start condition is met, the current a dditional preamble byte is completely sent before the transmi ssion of the next packet (i.e. programmed preamble) is started. 5.5.4. rx processing in rx mode the packet handler extracts the user pay load to the fifo by performing the following operat ions: receiving the preamble and stripping it off. detecting the sync word and stripping it off. optional dc-free decoding of data. optionally checking the address byte. optionally checking crc and reflecting the result on crc_status bit and crc_ok irq source. only the payload (including optional address and le ngth fields) is made available in the fifo. payload_ready and crc_ok interrupts (the latter onl y if crc is enabled) can be generated to indicate t he end of the packet reception.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 52 of 92 www.semtech.com by default, if the crc check is enabled and fails f or the current packet, then the fifo is automatical ly cleared and neither of the two interrupts are generated and new packet reception is started. this autoclear functi on can be disabled via pktparam_crc_autoclr bit and, in this case, even if crc fails, the fifo is not cleared an d only payload_ready irq source is asserted. once fully received, the payload can also be fully or partially retrieved in stby mode via pktparam_fifo_stby_access. at the end of the recept ion, although the fifo automatically stops being fi lled, it is still up to the user to explicitly exit rx mode if required. (e.g. go to stby to get payload). fifo mu st be empty for a new packet reception to start. 5.5.5. packet filtering SX1211s packet handler offers several mechanisms f or packet filtering ensuring that only useful packe ts are made available to the uc, reducing significantly system power consumption and software complexity. 5.5.5.1. sync word based sync word filtering/recognition is automatically en abled in packet mode. it is used for identifying th e start of the payload and also for network identification. as pre viously described, the sync word recognition block is configured (size, error tolerance, value) via rxparam_sync_siz e, rxparam_sync_tol and syncparam configuration registers. this information is used, both for appen ding sync word in tx, and filtering packets in rx. every received packet which does not start with thi s locally configured sync word is automatically dis carded and no interrupt is generated. when the sync word is detected, payload reception a utomatically starts and sync irq source is asserted . 5.5.5.2. address based address filtering can be enabled via the pktparam_a drs_filt bits. it adds another level of filtering, above sync word, typically useful in a multi-node networks whe re a network id is shared between all nodes (sync w ord) and each node has its own id (address). three address based filtering options are available : adrs_filt = 01: received address field is compared with internal register node_adrs. if they match th en the packet is accepted and processed, otherwise it is d iscarded. adrs_filt = 10: received address field is compared with internal register node_adrs and the constant 0x00. if either is a match, the received packet is accepted and processed, otherwise it is discarded. this addi tional check with a constant is useful for implementing br oadcast in a multi-node networks. adrs_filt = 11: received address field is compared with internal register node_adrs and the constants 0x00 & 0xff. if any of the three matches, then the receive d packet is accepted and processed, otherwise it is discarded. these additional checks with constants a re useful for implementing broadcast commands of al l nodes. please note that the received address byte, as part of the payload, is not stripped off the packet and is made available in the fifo. in addition, node_adrs and a drs_filt only apply to rx. on tx side, if address f iltering is expected, the address byte should simply be put int o the fifo like any other byte of the payload. 5.5.5.3. length based in variable length packet mode, pktparam_payload_le ngth must be programmed with the maximum length permitted. if received length byte is smaller than this maximum then the packet is accepted and proces sed, otherwise it is discarded.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 53 of 92 www.semtech.com please note that the received length byte, as part of the payload, is not stripped off the packet and is made available in the fifo. to disable this function the user should set the va lue of the pktparam_payload_length to the value of the fifo size selected. 5.5.5.4. crc based the crc check is enabled by setting bit pktparam_cr c_on. it is used for checking the integrity of the message. on tx side a two byte crc checksum is calculated o n the payload part of the packet and appended to th e end of the message. on rx side the checksum is calculated on the recei ved payload and compared with the two checksum byte s received. the result of the comparison is stored in the pktparam_crc_status bit and crc_ok irq source. by default, if the crc check fails then the fifo is automatically cleared and no interrupt is generate d. this filtering function can be disabled via pktparam_crc_autoclr b it and in this case, even if crc fails, the fifo is not cleared and only payload_ready interrupt goes high. please note that in both cases, the two crc checks um bytes are stripped off by the packet handler and only the payload is made available in the fifo. the crc is based on the ccitt polynomial as shown i n figure 45. this implementation also detects error s due to leading and trailing zeros. x 14 x 13 x 12 x 11 x 5 x 0 x 15 crc polynomial =x 16 + x 12 + x 5 + 1 * * * x 4 * * * data input figure 45: crc implementation 5.5.6. dc-free data mechanisms the payload to be transmitted may contain long sequ ences of 1s and 0s, which introduces a dc bias in the transmitted signal. the radio signal thus produced has a non uniform power distribution over the occup ied channel bandwidth. it also introduces data dependencies in the normal operation of the demodulator. thus it is useful if the transmitted data is random and dc free. for such purposes, two techniques are made availabl e in the packet handler: manchester encoding and da ta whitening. please note that only one of the two met hods should be enabled at a time. 5.5.6.1. manchester encoding manchester encoding/decoding is enabled by setting bit pktparam_manchester_on and can only be used in packet mode. the nrz data is converted to manchester code by cod ing 1 as 10 and 0 as 01. in this case, the maximum chip rate is the maximum bit rate given in the specifications section and th e actual bit rate is half the chip rate.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 54 of 92 www.semtech.com manchester encoding and decoding is only applied to the payload and crc checksum while preamble and sy nc word are kept nrz. however, the chip rate from prea mble to crc is the same and defined by mcparam_br ( chip rate = bit rate nrz = 2 x bit rate manchester). manchester encoding/decoding is thus made transpare nt for the user, who still provides/retrieves nrz d ata to/from the fifo. ...sync payload... rf chips @ br ... 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 ... user/nrz bits manchester off ... 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 ... user/nrz bits manchester on ... 1 1 1 0 1 0 0 1 0 0 1 1 ... t 1/br 1/br figure 46: manchester encoding/decoding 5.5.6.2. data whitening another technique called whitening or scrambling is widely used for randomizing the user data before r adio transmission. the data is whitened using a random sequence on the tx side and de-whitened on the rx s ide using the same sequence. comparing to manchester techniqu e it has the advantage of keeping nrz datarate i.e. actual bit rate is not halved. the whitening/de-whitening process is enabled by se tting bit pktparam_whitening_on. a 9-bit lfsr is us ed to generate a random sequence. the payload and 2-byte crc checksum is then xored with this random sequenc e as shown in figure 47. the data is de-whitened on t he receiver side by xoring with the same random seq uence. payload whitening/de-whitening is thus made transpa rent for the user, who still provides/retrieves nrz data to/from the fifo. x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 x 8 l f s r p o ly n o m ia l = x 9 + x 5 + 1 t ran sm it d ata w hite ne d d ata figure 47: data whitening 5.5.7. interrupt signal mapping tables below give the description of the interrupts available in packet mode.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 55 of 92 www.semtech.com table 23: interrupt mapping in rx and stby in packe t mode rx_stby_irq_x rx stby 00 (d) payload_ready - 01 write_byte - 10 /fifoempty /fifoempty irq_0 11 sync or adrs_match* - 00 (d) crc_ok - 01 fifofull fifofull 10 rssi - irq_1 11 fifo_threshold fifo_threshold *the latter if address filtering is enabled tx tx_start_irq_0=0 (d) fifo_threshold irq_0 tx_start_irq_0=1 /fifoempty tx_irq_1=0 (d) fifofull irq_1 tx_irq_1=1 tx_done table 24: interrupt mapping in tx packet mode 5.5.8. uc connections uc sx 1211 irq_0 irq_1 nss_config sck mosi miso nss_data figure 48: uc connections in packet mode note that depending upon the application, some uc c onnections may not be needed: irq_0: if none of the relevant irq sources are use d. in this case, leave floating. irq_1: if none of the relevant irq sources are use d. in this case, leave floating. miso: if no read register access is needed and the chip is used in tx mode only. in this case, pull u p to vdd through a 100 k resistor. in addition, data pin (unused in packet mode) shoul d be pulled-up to vdd through a 100 k resistor. please refer to table 13 for the SX1211s pin confi guration.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 56 of 92 www.semtech.com 5.5.9. packet mode example configure all data processing related registers li sted below appropriately. in this example we assume crc is enabled with autoclear on. table 25: relevant configuration registers in packe t mode (data processing related only) tx rx description data_mode_x x x defines data operation mode ( packet) fifo_size x x defines fifo size mcparam fifo_thresh x x defines fifo threshold rx_stby_irq_0 x defines irq_0 source in rx & stby modes rx_stby_irq_1 x defines irq_1 source in rx & stby modes tx_irq_1 x defines irq_1 source in tx mode irqparam tx_start_irq_0 x defines tx start condition and ir q_0 source sync_size x x defines sync word size rxparam sync_tol x defines the error tolerance on sync wor d detection syncparam sync_value x x defines sync word value manchester_on x x enables manchester encoding/decod ing payload_length x (1) x length in fixed format, max rx length in variable format node_adrs x defines node address for rx address fi ltering pkt_format x x defines packet format (fixed or vari able length) preamble_size x defines the size of preamble to be transmitted whitening_on x x enables whitening/de-whitening pro cess crc_on x x enables crc calculation/check adrs_filt x enables and defines address filtering crc_autoclr x enables fifo autoclear if crc failed pktparam fifo_stby_access x x defines fifo access in stby mo de (1) fixed format only tx mode : program tx start condition and irqs: start tx when fifo not empty (tx_start_irq_0=1) and irq_1 mapped to tx_done (tx_irq_1=1) go to stby mode write all payload bytes into fifo (fifo_stby_acces s=0, stby interrupts can be used if needed) go to tx mode. when tx is ready (automatically han dled) tx starts (tx_start_irq_0=1). wait for tx_done interrupt (+1 bit period) go to sleep mode rx mode : program rx/stby interrupts: irq_0 mapped to /fifoe mpty (rx_stby_irq_0=10) and irq_1 mapped to crc_ok (rx_stby_irq_1=00) go to rx (note that rx is not ready immediately, s ee section 7.3.1 wait for crc_ok interrupt go to stby read payload bytes from fifo until /fifoempty goes low. (fifo_stby_access =1) go to sleep mode 5.5.10. additional information if the number of bytes filled for transmission is g reater than the actual length of the packet to be t ransmitted and tx_start_irq_0 = 1, then the fifo is cleared after the packet has been transmitted. thus the extra byt es in the
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 57 of 92 www.semtech.com fifo are lost. on the other hand if tx_start_irq_0 = 0 then the extra bytes are kept into the fifo. th is opens up the possibility of transmitting more than one packe t by filling the fifo with multiple packet messages . it is not possible to receive multiple packets. onc e a packet has been received and filled into the fi fo all its content needs to be read i.e. the fifo must be empt y for a new packet reception to be initiated. the payload_ready interrupt goes high when the last payload byte is available in the fifo and remains high until all its data are read. similar behavior is applicab le to adrs_match and crc_ok interrupts. the crc result is available in the crc_status bit a s soon as the crc_successful and payload_ready inte rrupt sources are triggered. in rx mode, crc_status is cl eared when the complete payload has been read from the fifo. if the payload is read in stby mode, then crc _status is cleared when the user goes back to rx mo de and a new sync word is detected. the fifo_fill_method and fifo_fill bits dont have any meaning in the packet mode and should be set to their default values only.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 58 of 92 www.semtech.com 6. configuration and status registers 6.1. general description table 26 sums-up the control and status registers o f the SX1211: table 26: registers list name size address description mcparam 13 x 8 0 - 12 main parameters common to tra nsmit and receive modes irqparam 3 x 8 13 - 15 interrupt registers rxparam 6 x 8 16 - 21 receiver parameters syncparam 4 x 8 22 C 25 pattern txparam 1 x 8 26 transmitter parameters oscparam 1 x 8 27 crystal oscillator parameters pktparam 4 x 8 28 - 31 packet handler parameters 6.2. main configuration register - mcparam the detailed description of the mcparam register is given in table 27. table 27: mcparam register description name bits address (d) rw description chip_mode 7-5 0 r/w transceiver mode: 000 sleep mode - sleep 001 stand-by mode - stby (d) 010 frequency synthesizer mode - fs 011 receive mode - rx 100 transmit mode - tx freq_band 4-3 0 r/w frequency band: 00 902 C 915 mhz 01 915 C 928 mhz (d) 10 950 C 960 mhz or 863 - 870 mhz (application circui t dependant) vco_trim 2-1 0 r/w fine vco trimming: 00 vtune determined by tank inductors values (d) 01 vtune + 60 mv typ. 10 vtune + 120 mv typ. 11 vtune + 180 mv typ. rps_select 0 0 r/w selection between the two sets of frequency divider s of the pll, ri/pi/si 0 r1/p1/s1 selected(d) 1 r2/p2/s2 selected modul_select 7-6 1 r/w modulation type: 01 ook 10 fsk (d) data_mode_0 5 1 r/w data operation mode lsb (refer to data_mode_1 (bit 2 addr 1) ook_thresh_type 4-3 1 r/w ook demodulator threshold type: 00 fixed threshold mode 01 peak mode (d) 10 average mode 11 reserved
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 59 of 92 www.semtech.com data_mode_1 2 1 r/w data operation modes msb. cf. data_mode_0 (bit 5 a ddr 1) data_mode_1 bit 2 addr 1 data_mode_0 bit 5 addr 1 data operation mode 0 0 continuous (d) 0 1 buffered 1 x packet if_gain 1-0 1 r/w gain on the if chain: 00 maximal gain (0db) (d) 01 -4.5 db 10 -9db 11 -13.5 db freq_dev 7-0 2 r/w single side frequency deviation in fsk transmit mod e: refer to sections 3.3.4 and 3.3.5 fdev = 1) (d 32 + xtal f , 0 d 255, where d is the value in the register. (d): d = 00000011 => fdev = 100 khz res 7 3 r/w reserved (d): 0 br 6-0 3 r/w bit rate = 1) (c 64 + xtal f , 0 c 127, where c is the value in the register. (d): c = 0000111 => bit rate = 25 kb/s nrz ook_ floor_thresh 7-0 4 r/w floor threshold in ook rx mode. by default 6 db. (d): 00001100 assuming 0.5 db rssi step fifo_size 7:6 5 r/w fifo size selection: 00 16 bytes (d) 01 32 bytes 10 48 bytes 11 64 bytes fifo_thresh 5-0 5 r/w fifo threshold for interrupt source (cf section 5.2 .2.3) (d): b = 001111 r1 7-0 6 r/w r counter, active when rps_select=0 (d):77h; default values of r1, p1, s1 generate 915. 0 mhz in fsk mode p1 7-0 7 r/w p counter, active when rps_select=0 (d): 64h; default values of r1, p1, s1 generate 915 .0 mhz in fsk mode s1 7-0 8 r/w s counter, active when rps_select=0 (d): 32h; default values of r1, p1, s1 generate 915 .0 mhz in fsk mode r2 7-0 9 r/w r counter, active when rps_select=1 (d): 74h; default values of r2, p2, s2 generate 920 .0 mhz in fsk mode p2 7-0 10 r/w p counter, active when rps_select=1 (d): 62h; default values of r2, p2, s2 generate 920 .0 mhz in fsk mode s2 7-0 11 r/w s counter, active when rps_select=1 (d): 32h; default values of r2, p2, s2 generate 920 .0 mhz in fsk mode res 7-5 12 r/w reserved (d): 001 pa_ramp 4-3 12 r/w ramp control of the rise and fall times of the tx p a regulator output voltage in ook mode: 00 3us 01 8.5 us 10 15 us 11 23 us (d) res 2-0 12 r/w reserved (d):000
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 60 of 92 www.semtech.com 6.3. interrupt configuration parameters - irqparam the detailed description of the irqparam register i s given in table 28. table 28: irqparam register description name bits address (d) rw description rx_stby_irq_0 7-6 13 r/w irq_0 source in rx and standby modes: if data_mode(1:0) = 00 (continuous mode): 00 sync (d) 01 rssi 10 sync 11 sync if data_mode(1:0) = 01 (buffered mode): 00 - (d) 01 write_byte 10 /fifoempty* 11 sync if data_mode(1:0) = 1x (packet mode): 00 payload_ready (d) 01 write_byte 10 /fifoempty* 11 sync or adrs_match (the latter if address filterin g is enabled) *also available in standby mode (cf sections 5.4.4 and 5.5.7) rx_stby_irq_1 5-4 13 r/w irq_1 source in rx and standby modes: if data_mode(1:0) = 00 (continuous mode): xx dclk if data_mode(1:0) = 01 (buffered mode): 00 - (d) 01 fifofull* 10 rssi 11 fifo_threshold* if data_mode(1:0) = 1x (packet mode): 00 crc_ok (d) 01 fifofull* 10 rssi 11 fifo_threshold* *also available in standby mode (cf sections 5.4.4 and 5.5.7) tx_irq_1 3 13 r/w irq_1 source in tx mode: if data_mode(1:0) = 00 (continuous mode): x dclk if data_mode(1:0) = 01 (buffered mode) or 1x (packe t mode): 0 fifofull (d) 1 tx_done fifofull 2 13 r fifofull irq source goes high when fifo is full. /fifoempty 1 13 r /fifoempty irq source goes low when fifo is empty fifo_overrun_clr 0 13 r/w/ c goes high when an overrun error occurred. writing a 1 clears flag and fifo fifo_fill_method 7 14 r/w fifo filling method (buff ered mode only):
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 61 of 92 www.semtech.com 0 automatically starts when a sync word is detected (d) 1 manually controlled by fifo_fill fifo_fill 6 14 r/w/ c fifo filling status/control (buffered mode only): if fifo_fill_method = 0: (d) goes high when fifo is being filled (sync word has been detected) writing 1 clears the bit and waits for a new sync word (if fifo_overrun_clr=0) if fifo_fill_method = 1: 0 stop filling the fifo 1 start filling the fifo tx_done 5 14 r tx_done irq source goes high when the last bit has left the shift regi ster. tx_start_irq_0 4 14 r/w tx start condition and irq_0 source: if data_mode(1:0) = 01 (buffered mode): 0 tx starts if fifo is full, irq_0 mapped to /fifoem pty (d) 1 tx starts if fifo is not empty, irq_0 mapped to /f ifoempty if data_mode(1:0) = 1x (packet mode): 0 start transmission when the number of bytes in fif o is greater than or equal to the threshold set by mcparam_fifo_thresh p arameter (cf section 5.2.2.3), irq_0 mapped to fifo_threshold (d) 1 tx starts if fifo is not empty, irq_0 mapped to /f ifoempty res 3 14 r/w (d): 0, should be set to 1. note: 0 disables the rssi irq source. it can be l eft enabled at any time, and the user can choose to map this interrupt to irq0/i rq1 or not. rssi_irq 2 14 r/w/ c rssi irq source: goes high when a signal above rssi_irq_thresh is de tected writing 1 clears the bit pll_locked 1 14 r/w/ c pll status: 0 not locked 1 locked writing a 1 clears the bit pll_lock_en 0 14 r/w pll_lock detect flag mapped to pin 23: 0 lock detect disabled, pin 23 is high-z 1 lock detect enabled(d) rssi_irq_thresh 7-0 15 rssi threshold for interrupt (coded as rssi) (d): 00000000
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 62 of 92 www.semtech.com 6.4. receiver configuration parameters - rxparam the detailed description of the rxparam register is given in table 29. table 29: rxparam register description name bits address (d) rw description passivefilt 7-4 16 r/w typical single sideband bandwidth of the passive lo w-pass filter. passivefilt = 0000 65 khz 0001 82 khz 0010 109 khz 0011 137 khz 0100 157 khz 0101 184 khz 0110 211 khz 0111 234 khz 1000 262 khz 1001 321 khz 1010 378 khz (d) 1011 414 khz 1100 458 khz 1101 514 khz 1110 676 khz 1111 987 khz butterfilt 3-0 16 r/w sets the receiver bandwidth. for bw information ple ase refer to sections 3.4.5 (fsk) and 3.4.6 (ook). 8 ) ( 1 . 8 . 12 . 200 0 butterfilt val mhz mhz f khz f f xtal c + + = (d): 0011 => f c Cf 0 = 100 khz polypfilt_center 7-4 17 r/w central frequency of the polyphase filter (100khz r ecommended): 8 ) _ ( 1 . 8 . 12 . 200 0 center polypfilt val mhz mhz f khz f xtal + = (d):0011 => f 0 = 100 khz res 3-0 17 r/w reserved (d): 1000 polypfilt_on 7 18 r/w enable of the polyphase filter, in ook rx mode: 0 off (d) 1 on bitsync_off 6 18 r/w bit synchronizer: control in continuous rx mode: 0 on (d) 1 off sync_on 5 18 r/w sync word recognition: 0 off (d) 1 on sync_size 4-3 18 r/w sync word size: 00 8 bits 01 16 bits 10 24 bits 11 32 bits (d) sync_tol 2-1 18 r/w number of errors tolerated in the sync word recogni tion: 00 0 error (d) 01 1 error 10 2 errors 11 3 errors res 0 18 r/w reserved (d):0
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 63 of 92 www.semtech.com name bits address (d) rw description res 7-0 19 r/w reserved (d): 00000111 rssi_val 7-0 20 r rssi output, 0.5 db / bit note: read-only (not to be written) ook_thresh_step 7-5 21 r/w size of each decrement of the rssi threshold in the ook demodulator 000 0.5 db (d) 100 3.0 db 001 1.0 db 101 4.0 db 010 1.5 db 110 5.0 db 011 2.0 db 111 6.0 db ook_thresh_dec _period 4-2 21 r/w period of decrement of the rssi threshold in the oo k demodulator: 000 once in each chip period (d) 001 once in 2 chip periods 010 once in 4 chip periods 011 once in 8 chip periods 100 twice in each chip period 101 4 times in each chip period 110 8 times in each chip period 111 16 times in each chip period ook_avg_thresh _cutoff 1-0 21 r/w cutoff frequency of the averaging for the average m ode of the ook threshold in demodulator 00 f c br / 8. (d) 01 reserved 10 reserved 11 f c br / 32. 6.5. sync word parameters - syncparam the detailed description of the syncparam register is given in table 30. table 30: syncparam register description name bits address (d) rw description sync_value(31:24) 7-0 22 r/w 1 st byte of sync word (d): 00000000 sync_value(23:16) 7-0 23 2 nd byte of sync word (only used if sync_size 00) (d): 00000000 sync_value(15:8) 7-0 24 3 rd byte of sync word (only used if sync_size = 1x) (d): 00000000 sync_value(7:0) 7-0 25 4 th byte of sync word (only used if sync_size = 11) (d): 00000000
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 64 of 92 www.semtech.com 6.6. transmitter parameters - txparam the detailed description of the txparam register is given in table 31. table 31: txparam register description name bits address (d) rw description interpfilt 7-4 26 r/w tx interpolation filter cut o ff frequency: 8 ) ( 1 . 8 . 12 . 200 tx interpfilt val mhz mhz f khz fc xtal + = (d): 0111 => f c = 200 khz pout 3-1 26 r/w tx output power (1 step 3 db): 000 13 dbm 001 13 dbm -1 step (d) 010 13 dbm C 2 steps 011 13 dbm C 3 steps 100 13 dbm C 4 steps 101 13 dbm C 5 steps 110 13 dbm C 6 steps 111 13 dbm C 7 steps res 0 26 r/w reserved (d): 0 6.7. oscillator parameters - oscparam the detailed description of the oscparam register i s given in table 32. table 32: oscparam register description name bits address (d) rw description clkout_on 7 27 r/w clkout control 0 disabled 1 enabled, clk frequency set by clkout_freq (d) clkout_freq 6-2 27 r/w frequency of the signal prov ided on clkout: xtal f fclkout = if clkout_freq = 00000 freq clkout f fclkout xtal _ 2 = otherwise (d): 01111 (= 427 khz) res 1-0 27 r/w reserved (d): 00
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 65 of 92 www.semtech.com 6.8. packet handling parameters C pktparam the detailed description of the pktparam register i s given in table 33. table 33: pktparam register description name bits address (d) rw description manchester_on 7 28 r/w enable manchester encoding/d ecoding: 0 off (d) 1 on payload_length 6-0 28 r/w if pkt_format=0, payload length. if pkt_format=1, max length in rx, not used in tx. (d): 0000000 node_adrs 7-0 29 r/w nodes local address for filte ring of received packets. (d): 00h pkt_format 7 30 r/w packet format: 0 fixed length (d) 1 variable length preamble_size 6-5 30 r/w size of the preamble to be transmitted: 00 1 byte 01 2 bytes 10 3 bytes (d) 11 4 bytes whitening_on 4 30 r/w whitening/dewhitening process : 0 off (d) 1 on crc_on 3 30 r/w crc calculation/check: 0 off 1 on (d) adrs_filt 2-1 30 r/w address filtering of received packets: 00 off (d) 01 node_adrs accepted, else rejected. 10 node_adrs & 0x00 accepted, else rejected. 11 node_adrs & 0x00 & 0xff accepted, else rejected. crc_status 0 30 r crc check result for current pack et (read only): 0 fail 1 pass crc_autoclr 7 31 r/w fifo auto clear if crc failed for current packet: 0 on (d) 1 off fifo_stby_access 6 31 r/w fifo access in standby mo de: 0 write (d) 1 read res 5-0 31 r/w reserved (d): 000000
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 66 of 92 www.semtech.com 7. application information 7.1. crystal resonator specification table 34 shows the crystal resonator specification for the crystal reference oscillator circuit of the SX1211. this specification covers the full range of operation of the SX1211 and is employed in the reference design (see section 7.5.3). table 34: crystal resonator specification name description min. typ. max. unit fxtal nominal frequency 9 12.800 15 mhz cload load capacitance for fxtal 10 15 16.5 pf rm motional resistance - - 100 ohms co shunt capacitance 1 - 7 pf d fxtal calibration tolerance at 25+/-3c -15 - +15 ppm d fxtal( d t) stability over temperature range [-40c ; +85c] -2 0 - +20 ppm d fxtal( d t) ageing tolerance in first 5 years -2 - +2 ppm/year note that the initial frequency tolerance, temperat ure stability and ageing performance should be chos en in accordance with the target operating temperature ra nge and the receiver bandwidth selected. 7.2. software for frequency calculation the r1, p1, s1, and r2, p2, s2 dividers are configu red over the spi interface and programmed by 8 bits each, at addresses 6 to 11. the frequency pairs may hence be switched in a single spi cycle. 7.2.1. gui to aid the user with calculating appropriate r, p a nd s values, software is available to perform the f requency calculation. the SX1211 pll frequency calculator so ftware can be downloaded from the semtech website. 7.2.2. .dll for automatic production bench the dynamically linked library (dll) used by the so ftware to perform these calculations is also provid ed, free of charge, to users, for inclusion in automatic produc tion testing. key benefits of this are: no hand trimming of the reference frequency requir ed: the actual reference frequency of the device un der test (dut) can be easily measured (e.g. from the clkout output of the SX1211) and the tool will calculate t he best frequencies to compensate for the crystal init ial error. channel plans can be calculated and stored in the applications memory, then adapted to the actual cr ystal oscillator frequency. 7.3. switching times and procedures as an ultra-low power device, the SX1211 can be con figured for low minimum average power consumption. to minimize consumption the following optimized transi tions between modes are shown.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 67 of 92 www.semtech.com 7.3.1. optimized receive cycle the lowest-power rx cycle is the following: SX1211 i dd time set SX1211 in standby mode wait for xo settling set SX1211 in fs mode wait for pll settling set SX1211 in rx mode wait for receiver settling iddr 3.0ma typ. iddfs 1.3ma typ. iddst 65ua typ. iddsl 100na typ. wait ts_os c wait ts_fs wait ts_re receiver is ready : -rssi sampling is valid after a 1/fdev period -received data is valid SX1211 can be put in any other mode rx time figure 49: optimized rx cycle note: if the lock detect indicator is available on an external interrupt pin of the companion uc, it c an be used to optimize ts_fs, without having to wait the maximum specified ts_fs.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 68 of 92 www.semtech.com 7.3.2. optimized transmit cycle SX1211 i dd time set SX1211 in standby mode wait for xo settling set SX1211 in fs mode wait for pll settling set SX1211 in tx mode packet mode starts its operation iddt 16ma typ. @1dbm iddfs 1.3ma typ. iddst 65ua typ. iddsl 100na typ. wait ts_os c wait ts_fs wait ts_tr data transmission can start in continuous and buffered modes SX1211 can be put in any other mode tx time figure 50: optimized tx cycle note: as stated in the preceding section, ts_fs tim e can be improved by using the external lock detect or pin as external interrupt trigger.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 69 of 92 www.semtech.com 7.3.3. transmitter frequency hop optimized cycle SX1211 i dd time SX1211 is in tx mode on channel 1 (r1/p1/s1) SX1211 is now ready for data transmission iddt 16ma typ. @1dbm iddfs 1.3ma typ. wait ts_hop wait ts_tr set SX1211 back in tx mode 1. set r2/p2/s2 2. set SX1211 in fs mode, change mcparam_band if needed, then switch from r1/p1/s1 to r2/p2/s2 figure 51: tx hop cycle
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 70 of 92 www.semtech.com 7.3.4. receiver frequency hop optimized cycle SX1211 i dd time SX1211 is in rx mode on channel 1 (r1/p1/s1) SX1211 is now ready for data reception iddr 3ma typ iddfs 1.3ma typ. wait ts_hop wait ts_re set SX1211 back in rx mode 1. set r2/p2/s2 2. set SX1211 in fs mode, change mcparam_band if needed, then switch from r1/p1/s1 to r2/p2/s2 figure 52: rx hop cycle note: it is also possible to move from one channel to the other one without having to switch off the r eceiver. this method is faster, and overall draws more current. f or timing information, please refer to ts_re_hop on table 8.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 71 of 92 www.semtech.com 7.3.5. rx tx and tx rx jump cycles SX1211 i dd time SX1211 is in rx mode set SX1211 in tx mode SX1211 is now ready for data transmission iddr 3.0ma typ. wait ts_tr iddt 16ma typ. @1dbm set SX1211 in rx mode wait ts_re SX1211 is ready to receive data figure 53: rx tx rx cycle
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 72 of 92 www.semtech.com 7.4. reset of the chip a power-on reset of the SX1211 is triggered at powe r up. additionally, a manual reset can be issued by controlling pin 13. 7.4.1. por if the application requires the disconnection of vd d from the SX1211, despite of the extremely low sle ep mode current, the user should wait for 10 ms from of the end of the por cycle before commencing communicati ons over the spi bus. pin 13 (test8) should be left floating during the por sequence. wait for 10 ms vdd pin 13 (output) chip is ready from this point on undefined figure 54: por timing diagram please note that any clkout activity can also be us ed to detect that the chip is ready. 7.4.2. manual reset a manual reset of the SX1211 is possible even for a pplications in which vdd cannot be physically disco nnected. pin 13 should be pulled high for a hundred microsec onds, and then released. the user should then wait for 5 ms before using the chip. vdd > 100 u s chip is ready from this point on pin 13 (input) high-z high-z 1 wait for 5 ms figure 55: manual reset timing diagram please note that while pin 13 is driven high, an ov er current consumption of up to ten milliamps can b e seen on vdd.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 73 of 92 www.semtech.com 7.5. reference design it is recommended that this reference design (i.e. schematics, placement, layout, bom,) is replicated in the final application board to guarantee optimum performance. 7.5.1. application schematic figure 56: reference design circuit schematic the reference design area is represented by the das hed rectangle. c12 is a dc blocking capacitor which protects the saw filter. it has been added for debug purpose s could be removed for a direct antenna connection if there is no dc bias is expected at the antenna port. please note that c10 and c11 are not used. 7.5.2. pcb layout as illustrated in figures below, the layout has the following characteristics: very compact (9x19mm) => can be easily inserted ev en on very small pcbs standard pcb technology (2 layers, 1.6mm, std via & clearance) => low cost its performance is quasi-insensitive to dielectric thickness => minimal design effort to transfer to other pcb technologies (thickness, # of layers, etc...)
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 74 of 92 www.semtech.com the layers description is illustrated in figure 57: signal (35um) isolation (fr4, 1.6mm) ground plane figure 57: reference designs stackup the layout itself is illustrated in figure 58. plea se contact semtech for gerber files. 19mm 9mm figure 58: reference design layout (top view) 7.5.3. bill of material table 35: reference design bom value ref 868mhz 915mhz tol (+/-) techno size comment u1 SX1211 - transceiver ic tqfn-32 - u2 869 mhz 915 mhz - saw filter 3.8*3.8 mm plotted in section 7.5.4 q1 12.8 mhz 15 ppm at 25c 20 ppm over -40/+85c 2ppm/year max at-cut 5.0*3.2 mm fundamental, cload=15 pf r1 1 1% - 0402 pa regulator r2 6.8 k 1% - 0402 loop filter c1 1uf 15% x5r 0402 vdd decoupling c2 1uf 15% x5r 0402 top regulator decoupling c3 220 nf 10% x7r 0402 digital regulator decoupling c4 47 nf 10% x7r 0402 pa regulator decoupling c5 100 nf 10% x7r 0402 vco regulator decoupling c6 10 nf 10% x7r 0402 loop filter c7 680 pf 5% npo 0402 loop filter c8 1.8 pf 0.25 pf npo 0402 matching c9 22 pf 5% npo 0402 dc block and l4 adjust l1, l2 8.2 nh 6.8 nh 0.2 nh wire wound 0402 vco tan k inductors l3 100 nh 5% wire wound 0402 pa choke l4 8.2 nh 5% multilayer 0402 matching c10, c11 nc - - 0402 - c12* 47pf 5% npo 0402 dc block *not part of the ref. design (not required for dire ct antenna connection). note: for battery powered applications, a high valu e capacitance should be implemented in parallel wit h c1 (typically 10 f) to offer a low impedance voltage source during startup sequences.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 75 of 92 www.semtech.com 7.5.4. saw filter plot the following screenshot shows the plot of the saw filter used on the reference design: -80 -70 -60 -50 -40 -30 -20 -10 0 400 600 800 1000 1200 1400 1600 1800 2000 frequency [mhz] attenuation [db] figure 59: 915 mhz saw filter plot -80 -70 -60 -50 -40 -30 -20 -10 0 400 600 800 1000 1200 1400 1600 1800 2000 frequency [mhz] attenuation [db] figure 60: 869 mhz saw filter plot 7.5.5. ordering information for tools the modules described in section 7.5 can be ordered through your semtech representative for evaluation purpose: table 36: tools ordering information part number description sm1211e868 2 layer rf module, 868 mhz band sm1211e915 2 layer rf module, 915 mhz band SX1211sk868 full evalulation kit, including 2 sm121 1e868, controller boards, antennas and cables SX1211sk915 full evalulation kit, including 2 sm121 1e915, controller boards, antennas and cables
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 76 of 92 www.semtech.com 7.6. reference design performance all the measurements visible on section 7.6 typical figures obtained under the following conditions, u nless otherwise noted: nominal vdd = 3.3 v tests performed at room temperature: 25c +/-3c center frequency 869 mhz or 915 mhz {r, p, s} triplets are those calculated by the sof tware described in section 3.2.8. all register settings are default, except for thos e stated in the relevant sub-sections maximum output power programmed on pout tests all sensitivities are evaluated in continuous mode , demodulating a pn15 sequence, ber=0.1% fsk sensitivities measured at 25kbps, fdev=+/-50 k hz ook sensitivities measured at 8kbps, with fo=100 k hz. if2 set to 100 khz. on all adjacent channel rejection (acr), blocking and spurious response frequency tests, the unwanted signal is unmodulated. bill of materials as shown in section 7.5.3. in pa rticular, a saw filter is used (see its performance on section 7.5.4) the filter settings described on table 37 and tabl e 38 were used for the measurements of section 7.6. 5. table 37: fsk rx filters vs. bit rate rx 3 db bw bit rate fdev filter setting addr 16 fdev + br/2 programmed actual max. drift kbps +/- khz hex khz khz khz +/- ppm 100 200 ff 250 400 306 62 66.67 133 e9 166.7 250 214 53 50 100 d6 125 175 158 37 40 80 b5 100 150 137 41 33.33 67 a4 83.3 125 116 36 28.57 57 a3 71.4 100 96 27 25 50 a3 62.5 100 96 37 22.22 44 72 55.6 75 69 15 20 40 72 50 75 69 21 18.18 36 72 45.5 75 69 26 16.67 33 72 41.7 75 69 30 15.38 33 41 41 50 47 7 14.29 33 41 40.5 50 47 7 12.5 33 41 39.6 50 47 8 10 33 41 38.3 50 47 10 5 33 41 35.8 50 47 12 2 33 41 34.3 50 47 14 table 38: ook rx filters vs. bit rate rx 3 db bw bit rate f o + br filter setting addr 16 programmed actual max. drift kbps khz hex khz khz +/- ppm 16.67 117 c1 150 154 41 12.5 113 c1 150 154 46 9.52 110 a0 125 129 22 8 108 a0 125 129 23 4.76 105 a0 125 129 27 2.41 102 a0 125 129 30 1.56 102 a0 125 129 30
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 77 of 92 www.semtech.com 7.6.1. sensitivity flatness sensitivity over the frequency band -106.0 -104.0 -102.0 -100.0 -98.0 -96.0 -94.0 -92.0 -90.0 863 864 865 866 867 868 869 870 frequency [mhz] sensitivity @ ber=0.1% -2.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 saw ripple [db] sensitivity saw ripple figure 61: sensitivity across the 868 mhz band sensitivity over the frequency band -106.0 -104.0 -102.0 -100.0 -98.0 -96.0 -94.0 -92.0 -90.0 902 904 906 908 910 912 914 916 918 920 922 924 926 928 frequency [mhz] sensitivity [dbm] -2.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 saw ripple [db] sensitivity saw ripple figure 62: sensitivity across the 915 mhz band notes: measured in fsk mode only. ook sensitivity charact eristics will be similar. the sensitivity difference along the band remains inside the ripple performance of the saw filter (th e nominal passband of the 869 mhz saw filter is 868 C 870 mhz ) the saw filter ripple response is referenced to it s insertion loss at 869 mhz and 915 mhz for each fi lter.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 78 of 92 www.semtech.com 7.6.2. sensitivity vs. lo drift sensitivity loss vs. lo drift -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 -25 -20 -15 -10 -5 0 5 10 15 20 25 lo drift [khz] sensitivity loss [db] figure 63: fsk sensitivity loss vs. lo drift sensitivity loss vs. lo drift -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 -100 -80 -60 -40 -20 0 20 40 60 80 100 lo drift [khz] sensitivity loss [db] figure 64: ook sensitivity loss vs. lo drift notes: in fsk mode, the default filter setting (a3 at a ddress $16) is kept, leading to fc=96 khz typ. in ook mode, f3 is set at address $16, leading t o (fc-fo)=95 khz typ. the above ensures that the channel filter is wide enough, therefore characterizing the demodulator re sponse, and not the filter response.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 79 of 92 www.semtech.com 7.6.3. sensitivity vs. receiver bw sensitivity vs. fc -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 50 100 150 200 250 300 fc of active filter [khz] sensitivity improvement [db] => figure 65: fsk sensitivity vs. rx bw sensitivity change vs. (fc-fo) -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 0 50 100 150 200 250 300 350 fc-fo [khz] sensitivity improvement [db] => figure 66: ook sensitivity change vs. rx bw
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 80 of 92 www.semtech.com 7.6.4. sensitivity stability over temperature and v oltage sensitivity stability -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.10 2.40 2.70 3.00 3.30 3.60 vdd [v] sensitivity improvement [db] => 85c 25c 0c -40c figure 67: sensitivity stability note: the sensitivity performance is very stable over th e vdd range, and the effect of high temperature is minimal. 7.6.5. sensitivity vs. bit rate sensitivity change over br -8.0 -6.0 -4.0 -2.0 0.0 2.0 4.0 6.0 8.0 0 25 50 75 100 bit rate [kb/s] sensitivity improvement [db] => figure 68: fsk sensitivity vs. br
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 81 of 92 www.semtech.com sensitivity change over the br -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 1.5 4 6.5 9 11.5 14 16.5 bit rate [kbps] sensitivity improvement [db] => figure 69: ook sensitivity vs. br 7.6.6. adjacent channel rejection acr in fsk mode 0 10 20 30 40 50 60 70 -1000 -800 -600 -400 -200 0 200 400 600 800 1000 offset [khz] acr [db] figure 70: acr in fsk mode
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 82 of 92 www.semtech.com acr in ook mode -20 -10 0 10 20 30 40 50 60 -300 -200 -100 0 100 200 300 offset [khz] acr [db] figure 71: acr in ook mode notes: in fsk mode, the unwanted signal is unmodulated (a s described in the en 300-220 v2.1.1).co-channel rejection (ccr, offset = 0khz) is positive due to t he dc cancellation process of the zero-if architect ure in ook mode, the polyphase filter efficiency is li mited, thus limiting the adjacent channel rejection at 2xfo distance. 7.6.7. output power flatness pout over the frequency band 0.0 2.0 4.0 6.0 8.0 10.0 12.0 863 864 865 866 867 868 869 870 frequency [mhz] pout [dbm] -8.0 -6.0 -4.0 -2.0 0.0 2.0 4.0 saw ripple [db] pout saw ripple figure 72: pout for 869 mhz band operation
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 83 of 92 www.semtech.com pout over the frequency band 0.00 2.00 4.00 6.00 8.00 10.00 12.00 902 904 906 908 910 912 914 916 918 920 922 924 926 928 frequency [mhz] pout [dbm] -8.0 -6.0 -4.0 -2.0 0.0 2.0 4.0 saw ripple [db] pout saw ripple figure 73: pout for 915 mhz band operation notes: as noted in section 7.5.4, the 869 mhz saw filter does not cover the whole european 863 C 870 mhz frequency band when used in a 50 ohms environment. hence the output power degradation at the lowest frequencies. for applications in the 863 C 870 mhz band it is recommended that an appropriate saw filt er be implemented or that the saw response tuned by exter nal matching. the saw filter ripple references are the insertion loss of each saw at 869 mhz and 915 mhz. 7.6.8. pout and idd vs. pa setting pout & idd vs. txparam_pout setting -12.0 -8.0 -4.0 0.0 4.0 8.0 12.0 0 1 2 3 4 5 6 7 txparam_pout [d] pout [dbm] 10.00 12.00 14.00 16.00 18.00 20.00 22.00 24.00 26.00 28.00 pout idd figure 74: pout and idd at all pa settings, 869 mhz
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 84 of 92 www.semtech.com pout & idd vs. txparam_pout setting -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 0 1 2 3 4 5 6 7 txparam_pout [d] pout [dbm] 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 30.0 idd [ma] pout idd figure 75: pout and idd at all pa settings, 915 mhz note: +10dbm typ. output power is achievable, even at sa w filters output. 7.6.9. pout stability over temperature and voltage pout stability -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 2.1 2.4 2.7 3.0 3.3 3.6 vdd [v] pout improvement [db] => 85c 25c -40c 0c figure 76: pout stability the output power is not sensitive to the supply vol tage, and it decreases slightly when temperature ri ses.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 85 of 92 www.semtech.com 7.6.10. transmitter spectral purity figure 77: 869 mhz spectral purity dc-1ghz figure 78: 869 mhz spectral purity 1-6ghz
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 86 of 92 www.semtech.com 7.6.11. ook channel bandwidth the ook bit rate ranges form 1.56 to 16.7 kbps. it is interesting to note that, for the lowest bit rat es, a channel spacing approaching 200 khz is achievable: figure 79: ook spectrum - 2kbps figure 80: ook spectrum - 8kbps figure 81: ook spectrum - 16.7kbps notes: the test conditions are: fdev=100 khz, txparam_int erpfilt = 200 khz
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 87 of 92 www.semtech.com 7.6.12. fsk spectrum in europe figure 82 shows the minimal spectral occupation ach ievable in the european band, keeping in mind that the minimum frequency deviation that a SX1211 receiver can accept is 33 khz. if the companion receiver can bear smaller frequency deviations, the range of modulati on bandwidth can be further decreased. figure 82: fsk - 1.56kbps - +/-33 khz the default configuration of the SX1211 yields the bandwidth visible on figure 83: figure 83: fsk - 25 kbps - +/-50 khz figure 84 shows the maximal bit rate and frequency deviation that can fit in the 868 to 868.6 mhz euro pean sub- band: figure 84: fsk - 40 kbps - +/-40 khz
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 88 of 92 www.semtech.com 7.6.13. digital modulation schemes fcc part 15.247 allows for systems employing digita l modulation techniques to transmit up to 1 w, prov ided that the 6 db bandwidth of the signal is at least 500 kh z and that the power spectral density does not exce ed 8dbm in any 3 khz bandwidth. the SX1211 can actually meet these constraints whil st transmitting at the maximum output power of the device of typ. 10dbm, thanks to the built-in whitening proces s described in section 5.5.6.2: figure 85: dts 6db bandwidth figure 86: dts power spectral density conditions: pout = +10.6dbm fdev = +/-200khz br=100 kbps (chip rate=100kcps, as data whitening is enabled) packet mode, data whitening enabled note: manchester encoding allows meeting an even lo wer power spectral density, at the expense of the b it rate efficiency.
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 89 of 92 www.semtech.com 7.6.14. current stability over temperature and volt age tx mode current (max output power) 0.0 5.0 10.0 15.0 20.0 25.0 30.0 2.1 2.4 2.7 3.0 3.3 3.6 vdd [v] itx [ma] txlvl=000 85c 25c -40c 0c sleep mode current 0 200 400 600 800 1000 1200 2.1 2.4 2.7 3 3.3 3.6 vdd [v] isleep [na] 85c 25c 0c -40c standby mode current 0 10 20 30 40 50 60 70 80 90 100 2.1 2.4 2.7 3 3.3 3.6 vdd [v] istby [ua] 85c 25c 0c -40c fs mode current 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.1 2.4 2.7 3 3.3 3.6 vdd [v] ifs [ma] 85c 25c 0c -40c rx mode current 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 2.1 2.4 2.7 3 3.3 3.6 vdd [v] irx [ma] 85c 25c 0c -40c figure 87: idd vs. temp and vdd
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 90 of 92 www.semtech.com 8. packaging information 8.1. package outline drawing SX1211 is available in a 32-lead tqfn package as sh own in figure 88 below. figure 88: package outline drawing 8.2. pcb land pattern figure 89: pcb land pattern
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 91 of 92 www.semtech.com 8.3. tape & reel specification carrier tape reel tape width(w) pocket pitch (p) ao/bo ko reel size reel width min.trail er length min. leader length qty per reel 12 +/-0.3 8 +/-0.1 5.25 +/-0.2 1.10 +/-0.1 330.2 12.4 400 400 3000 notes: *all dimensions in mm *single sprock et holes direction of feed figure 90: tape & reel dimensions
SX1211 advanced communications & sensing rev 7 C sept 2 nd , 2008 page 92 of 92 www.semtech.com 9. revision history revision 5 increase maximum bit rate in fsk update minimum xo frequency add the manual reset description insert decoupling recommendation for battery operated systems add tools ordering information revision 6 update spi speed clarify default fc value in table 29 clarify miso state in spi timing figures improve esd rating description revision 7 describe pll_lock pin state in table 13 improve note in section 5.4.1 clarify table 5 measurement conditions clarify /fifoempty interrupt source behavior correct vtune in figure 5 adjust vco tuning range in section 3.2.5.2 10. contact information ? semtech 2008 all rights reserved. reproduction in whole or in pa rt is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believe d to be accurate and reliable and may be changed without notice. no liab ility will be accepted by the publisher for any con sequence of its use. publication thereof does not convey nor imply any l icense under patent or other industrial or intellec tual property rights. semtech. assumes no responsibility or liability wha tsoever for any failure or unexpected operation res ulting from misuse, neglect improper installation, repair or improper h andling or unusual physical or electrical stress in cluding, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. semtech products are not designed, intended, author ized or warranted to be suitable for use in life-support applications, devices or system s or other critical applications. inclusion of semtech products in such applications is understo od to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized appl ication, the customer shall indemnify and hold semtech and i ts officers, employees, subsidiaries, affiliates, a nd distributors harmless against all claims, costs damages and attorney fees which could arise. semtech corporation advanced communication and sensing products divisio n 200 flynn road, camarillo, ca 93012 phone (805) 498-2111 fax: (805) 498-3804

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